SVA assertions question

[sree205]

passing a parameter to an sva assertions

Hi all,
I'm trying to come up with an assertion using systemverilog with a small difference. a typical property is,

property p_tcnst;
@(posedge clk)
$fell (variable_name) |->
##tcnst $rose (variable_name);
end property

In this property, would it be possible to substitute the tcnst parameter with a RTL variable?

 

[ankurgupta74]

no. it is a constant.

 

[boardlanguage]

property p_tcnst;
@(posedge clk)
$fell (variable_name) |->
##[b]tcnst[/b] $rose (variable_name);
end property

You may already know this, but but tcnst can be a declared parameter or other compile-time constant. (it doesn't have to be a literal constant.)

parameter int blah_start = 94;
parameter int blah_end  = 121;

// tcnst = (#cycles) pulse-width between $fell and $rose
parameter int tcnst = blah_end - blah_start;

 

[sree205]

The problem is, even if tcnst is a parameter, i won't be able to change it at run time. i'm not able to change the tcnst value based on some RTL signal value.

 

[natg9]

Hi friends

i am looking for some material to study System Verilog Assertions
please share if you have any documents

thanks in advance

regards
natg