Aug 25, 2008 #1 sree205 Advanced Member level 1 Joined Mar 13, 2006 Messages 453 Helped 58 Reputation 116 Reaction score 25 Trophy points 1,308 Activity points 4,420 passing a parameter to an sva assertions Hi all, I'm trying to come up with an assertion using systemverilog with a small difference. a typical property is, property p_tcnst; @(posedge clk) $fell (variable_name) |-> ##tcnst $rose (variable_name); end property In this property, would it be possible to substitute the tcnst parameter with a RTL variable?
passing a parameter to an sva assertions Hi all, I'm trying to come up with an assertion using systemverilog with a small difference. a typical property is, property p_tcnst; @(posedge clk) $fell (variable_name) |-> ##tcnst $rose (variable_name); end property In this property, would it be possible to substitute the tcnst parameter with a RTL variable?
Aug 26, 2008 #2 A ankurgupta74 Newbie level 3 Joined Aug 25, 2008 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,289 no. it is a constant.
Aug 26, 2008 #3 B boardlanguage Full Member level 1 Joined Apr 6, 2007 Messages 96 Helped 7 Reputation 14 Reaction score 1 Trophy points 1,288 Activity points 2,083 Code: property p_tcnst; @(posedge clk) $fell (variable_name) |-> ##[b]tcnst[/b] $rose (variable_name); end property You may already know this, but but tcnst can be a declared parameter or other compile-time constant. (it doesn't have to be a literal constant.) Code: parameter int blah_start = 94; parameter int blah_end = 121; // tcnst = (#cycles) pulse-width between $fell and $rose parameter int tcnst = blah_end - blah_start;
Code: property p_tcnst; @(posedge clk) $fell (variable_name) |-> ##[b]tcnst[/b] $rose (variable_name); end property You may already know this, but but tcnst can be a declared parameter or other compile-time constant. (it doesn't have to be a literal constant.) Code: parameter int blah_start = 94; parameter int blah_end = 121; // tcnst = (#cycles) pulse-width between $fell and $rose parameter int tcnst = blah_end - blah_start;
Aug 27, 2008 #4 sree205 Advanced Member level 1 Joined Mar 13, 2006 Messages 453 Helped 58 Reputation 116 Reaction score 25 Trophy points 1,308 Activity points 4,420 The problem is, even if tcnst is a parameter, i won't be able to change it at run time. i'm not able to change the tcnst value based on some RTL signal value.
The problem is, even if tcnst is a parameter, i won't be able to change it at run time. i'm not able to change the tcnst value based on some RTL signal value.
Mar 16, 2009 #5 N natg9 Member level 3 Joined Jul 17, 2008 Messages 56 Helped 7 Reputation 14 Reaction score 0 Trophy points 1,286 Activity points 1,588 Hi friends i am looking for some material to study System Verilog Assertions please share if you have any documents thanks in advance regards natg
Hi friends i am looking for some material to study System Verilog Assertions please share if you have any documents thanks in advance regards natg