Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

some question about jtag - continuity test

Status
Not open for further replies.

xworld2008

Full Member level 4
Joined
Dec 13, 2002
Messages
231
Helped
18
Reputation
36
Reaction score
14
Trophy points
1,298
Activity points
1,801
some question about jtag

recently i read jtag document and have some question:
1. does use jtag to test continuity of pads at chip level , before we just use power off method to test continuity of pads
2. if use jtag to test continuity , how to generate pattern
3.at board level how to generate jtag pattern
please help me,
thanks
 

Colbhaidh

Full Member level 6
Joined
Aug 10, 2004
Messages
395
Helped
141
Reputation
280
Reaction score
98
Trophy points
1,308
Location
Scotland
Activity points
3,756
Re: some question about jtag

JTAG is not used to test continuity of Pads, the probe test on each IC would fail if there was a continuity problem. JTAG is much more complex than this.
It is typically a collection of logic arranged over the chip to cover as much area as possible without compromising the function f the chip. Streams of data are fed in through a serial connection and read out the other end. The data read out can determine if certain areas of the chip are not functioning correctly. This can be particularly useful for an analogue or RF IC where the ability to test the chip at wafr probe is limited due to high frequencies or noise etc.
The JTAG is digital and although the component blocks may have nothing to do with the IC's function, if something in the digital block is failing, chances are the chip will fail.
Another use for JTAG is where multiple IC's are stacked inside the same package e.g. a dense logic IC, and RF IC and a EEPROM IC for a cellular phone. If the package doesn't work then how d you know which IC is failing. They ay have come from different Fabs. JTAG can be used to determine which IC is faulty and who you can shout at !
 

Barry Pearson

Newbie level 5
Joined
Dec 3, 2009
Messages
8
Helped
5
Reputation
10
Reaction score
4
Trophy points
1,283
Location
Ireland
Activity points
1,343
I'm afarid I disagree somewhat with Colbhaidh.

JTAG is the acronym for Joint Test Action Group. It is alos known as boundary-scan
and was initially devised as a board-level test mechanism to test for defects in the
connections between ICs and not really within the ICs themselves. If a device is
compliant with the IEEE std 1149.1 then it is JTAG or more precisely boundary-scan
compliant and will include some test logic within the chip that allows you to drive
and sense values on device pins independantly of the core device logic.

You can indeed then use that logic to create board-level continuity tests.

However to back-up Colbhaidh a little the JTAG port has also been used for other
purposes sinces it's inception. Principally for programming of CPLDs and FPGAs
and also for accessing on-chip debug features of processors and DSPs typically.

To use the generic boundary-scan JTAG function for contiunuity testing there is now
some free software now available at www.jtaglive.com that works with Altera and
Xilinx interface cables. At the web-site www.boundary-scan.co.uk there is more
basic JTAG information

Good luck

Barry
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top