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JTAG TDI and TDO pins and its relation with Si and So pins

fragnen

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We have Scan in and Scan out pin in the top level rtl of the soc as Si and So pins respectively.

Do these Si and So pins are connected with TDI and TDO pins of JTAG of the chip respectively?
 
The JTAG was intended for boundary scan, but it is often also used for configuration, debug, programming, and so on. It is a standard, so the pins are:
  • TCK: JTAG clock
  • TMS: the mode/select signal
  • TDI: JTAG data in
  • TDO: JTAG data out
  • nTRST: the optional JTAG reset
You usually connect the components in series, one TDO goes to the next chip's TDI, in a chain. Then TMS, TCK and nTRST goes to all. This is the most common topology but there are other ways too.

Scan chain, now, is a whole different beast. These are used inhouse by the maker. So you often have:
  • SCANMODE: enters scan mode
  • SCANEN: selects scan shift
  • SI: scan data in
  • SO: scan data out
  • SCLK: scan clock
These pins usually do not show up in the documentation as they are handled before the chip goes to the customers. Only SCANMODE it is recommended to be a real pin. So, let's say it is a CPU, perhaps you use the UART pins for the scanin and scanout, a SPI clock as scan clock and so on. For scan mode then you just put it as a reserved pin on the package or perhaps even leave it as an non-bonded pad (floating inside the package). Some companies also make SCANMODE be a reserved JTAG command to save pins. The Genus manual has a suggestion to share scanin with TDI and scanout with TDO, but that is just one of the many ways to set this up. Being the test method is not published, you can find all kinds of ways.

This is a basic setup though, often a chip might have multiple scan chains to split up the chain, depending on how large is the design. The largest one I have dealt with had 17 pairs of SI and SO. The other pins were shared. But this is still assuming you have an old technology (perhaps over 110nm) and slow clock (under 20MHz). When this is not the case you might have to add more features:

  • if you are using a more advanced node, you might need at-speed testing, where your internal clock is used to do the scan launch/capture pulses
  • perhaps scan chain compression
  • perhaps have multiple clocks or enables
  • and so on
And then you might have other pins, like opcg_enable, compress_enable etc. Some people just go ahead and put the extra pins in a jtag interface too, so you wind up using the jtag to setup features and then the tester does the scan chain test.
 
The JTAG was intended for boundary scan, but it is often also used for configuration, debug, programming, and so on. It is a standard, so the pins are:
  • TCK: JTAG clock
  • TMS: the mode/select signal
  • TDI: JTAG data in
  • TDO: JTAG data out
  • nTRST: the optional JTAG reset

Can you please answer the following questions?

1. Do we generate ATPG patterns for boundary scan?

2. Do we definitely need these JTAG pins for ATPG of boundary scan cells?

3. Is it that main purpose of JTAG is to do ATPG for boundary of the chip?

4. Is not it that we always see the JTAG ports (TDI, TDO, TMS, TCK and optional TRST) at the boundary of the chip after the chip is realized on silicon and packaged to the customer as a chip I/O ?

Thanks for your earlier reply.
 
I think you are confusing two different tests. After the chip is made it will be sent to a testing house. There it will go through the tests using the automatic testers (ATPG). This usually includes:
  • scan chain
  • MBIST to test any SRAMs, flash, and other on chip memories
  • analog funtional testing and trimming, if any
  • perhaps an initial firmware programming, if needed
Now, the JTAG can be used for these tests just because the pins are there, in fact Genus can create a jtag module and add commands to create JTAG commands for scan compression, MBIST testing, etc. You can also tell Genus (or Synopsys design compiler or other tools) to just create or reuse any existing digital pins on the chip if you do not have a JTAG. This is very custom to each chip. If all you need is simple stuck-at-fault scan then you do not need JTAG, you could just reuse pins for, say, a SPI interface and have them become scan chain pins in test mode. For the analog tests, there is no real standard, so you need to come up with something, just make sure the test house can test it. Some test houses offer consulting and will help you plan how you want the chip to be tested and what is the best way to do it.

Now, the boundary scan itself will be used by whoever uses the chip. Genus will generate a BSDL file, which is used to describe the chip's interface. I do not know if there is anything newer out there, it is not my area, but that is the traditional way of doing boundary scan. Whatever ATPG software is used will take the multiple BSDL files, and perhaps other files and generate the patterns for the PCB test. The boundary scan test will use the boundary scan cells (which are modified IO cells) and shift a pattern into them, which will go from one chip to the next to make sure the PCB was built corectly. If you have JTAG compatible memories, you can also use the JTAG protocol to upload an initial firmware. So, for boundary scan test you will need the JTAG and boundary scan IO cells.

On your last question, yes, beign JTAG is usually used for board testing, so they will always be on the package. Chip test pins though may be on the package or may not be. Depends on the design and if the test house has prefers to test the chips on wafer level or on the packaged device. For example, a pin like scanmode I have seen it as a bonded pad (on the package) on some designs and as a non-bonded pad (unaccessible after packaging) on other chips.
 
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Thanks for the reply.

Answer to the last question is yes as clearly stated by you.

Below are the answers to the above questions after going through your reply.

Please correct the below answer if the answer is wrong. The answer is typed all in capital letters.


1. Do we generate ATPG patterns for boundary scan?

YES.

2. Do we definitely need these JTAG pins for ATPG of boundary scan cells?

YES.

3. Is it that main purpose of JTAG is to do ATPG for boundary of the chip?

YES.
--- Updated ---

glennramalho, Should we take the above 3 answers are correct?
 
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1) Yes, there is a ATPG pattern, but it is ATPG for PCB, so the patterns will be based on the PCB layout and the BSDL files for each IC on the PCB
2) yes, JTAG is an essential part of boundary scan
3) no. JTAG was designed for Boundary scan but today JTAG has many other uses. In fact I am working right now on a chip that has JTAG but does not have boundary scan. So, just because there is a JTAG port it does not mean the chip is compatible with boundary scan.
 
I think you are confusing two different tests.
What do you mean by two different tests? Do you want to mean one/first kind of test is testing the internals of the chip like the logic, memories inside the chip and the another/second kind is the boundary scan test and PCB test?

For the analog tests, there is no real standard, so you need to come up with something, just make sure the test house can test it. Some test houses offer consulting and will help you plan how you want the chip to be tested and what is the best way to do it.

Now, the boundary scan itself will be used by whoever uses the chip.
Do you want to mean that boundary scan are done by the customer or whoever uses that packaged chip? Are not the chip IO tested using boundary scan by in house testing where we test the internals of the chip like the internal logic, memories inside the chip?

There are few more questions as asked below:

1. What ATPG tools are used to generate ATPG patterns for boundary scan as we use Synopsys TetraMax, Mentor Graphics Tessent to generate ATPG for different faults for the Logic which is inside the chip?

2. Which tools are available to insert automatically DFT logic in a design to improve fault coverage/test coverage for different faults like stuck at faults, delay faults, bridging faults etc?
 
I guess one could use boundary scan to check the packaging on a chip, but I have seen people use other tests for that. They check the sink current, capacitance and so on. Perhaps in MCPs but I have no experience with them. Boundary scan was designed for PCB makers to test that the welding between the chip and the board was done right and that the wires were manufactrued corectly.

As for tools, in case of Cadence, Genus will synthesize the design and insert all the DFT structures needed, MBIST (they call it PMBIST), scan chain, and so on. Then Modus is used to generate the ATPG patterns for this. I did just skimmed through the Modus manual but I did not find much about the boundary scan, just that Cadence generates the boundary scan chain and is compatible with it. Genus will create the BSDL file that the PCB designer can use to test his board.

Synopsys does this via Design Compiler. It will synthesize the design and insert the DFT and Tetramax will generate the ATPG patterns. I do not know much of Mentor, I know there is Tessent but I have never used it.
--- Updated ---

I don't know what tools are used to generate the PCB boundary scan patterns. I have no experience in that area.
 
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