I have doubt that why do we need to do zero delay simulation ? even atpg tool generates pattern for design and we also improve the coverage. input pattern is generated and we also get the output pattern as per design. so that is expected output. so why it is necessary to do simulation as we get output as per design.
functional simulation is needed to check your logic is doing what you intend. If you jump direct to timing simulation or hardware testing then by sheer great luck it may pass. If it doesn't not pass you need to see inside what is breaking.
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ATPG generates test patterns, period. It will succeed whether the chip/design has bugs or not.
Someone still has to do regular RTL simulation and that cannot be done via ATPG.
The purpose of ATPG is making sure the part that gets manufactured performs exactly the way the hardware description language code instructed it to be made. It tells you nothing about how well the code does to meet the requirements the part was supposed to satisfy.
This means if there are any mistakes in your design, ATPG proves that the manufactured part has the same mistake.