Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

simulation- zero delay sim required if result is as expected per design?

Status
Not open for further replies.

CVAGHASIYA

Newbie
Joined
Dec 31, 2019
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
28
hello, I am beginner

I have doubt that why do we need to do zero delay simulation ? even atpg tool generates pattern for design and we also improve the coverage. input pattern is generated and we also get the output pattern as per design. so that is expected output. so why it is necessary to do simulation as we get output as per design.
 

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
5,948
Helped
1,172
Reputation
2,356
Reaction score
1,300
Trophy points
1,393
Location
California, USA
Activity points
32,348
How do you know you’re going to get the correct output if you don’t do a simulation?
 

CVAGHASIYA

Newbie
Joined
Dec 31, 2019
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
28
How do you know you’re going to get the correct output if you don’t do a simulation?
okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.
 
Last edited:

kaz1

Full Member level 3
Joined
Aug 15, 2019
Messages
183
Helped
14
Reputation
28
Reaction score
31
Trophy points
28
Location
UK
Activity points
1,244
functional simulation is needed to check your logic is doing what you intend. If you jump direct to timing simulation or hardware testing then by sheer great luck it may pass. If it doesn't not pass you need to see inside what is breaking.
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,321
Helped
389
Reputation
778
Reaction score
418
Trophy points
83
Activity points
12,077
okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.
?
ATPG generates test patterns, period. It will succeed whether the chip/design has bugs or not.
Someone still has to do regular RTL simulation and that cannot be done via ATPG.
 

dave_59

Advanced Member level 3
Joined
Dec 15, 2011
Messages
829
Helped
365
Reputation
734
Reaction score
359
Trophy points
1,353
Location
Fremont, CA, USA
Activity points
7,041
okk...it means Atpg tool doesn't give correct output ???
please solve my doubt.
The purpose of ATPG is making sure the part that gets manufactured performs exactly the way the hardware description language code instructed it to be made. It tells you nothing about how well the code does to meet the requirements the part was supposed to satisfy.

This means if there are any mistakes in your design, ATPG proves that the manufactured part has the same mistake.
 

song524

Newbie
Joined
Dec 31, 2021
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
17
Logic function has nothing to do with DFT
Simulation is to verify the function
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top