promach
Advanced Member level 4
I have two questions below for set_clock_gating_check command which is also highlighted in yellow below:
1. Why for OR and NOR gates, the setup check is performed with respect to the falling edge of the clock input ?
2. Why for OR gates, the non-controlling value is low ?
1. Why for OR and NOR gates, the setup check is performed with respect to the falling edge of the clock input ?
2. Why for OR gates, the non-controlling value is low ?
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