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Questions about A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops

promach

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For A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops ,
  1. Why Notice that since FF''' is oppositely clocked and its data is sampled at the clock’s falling edge, its clock enabling signal X''' must be negated. ?
  2. Why does the author state that : F''' is an ordinary FF where the internal XOR gate is connected between D''' and Q'''. ?



 

promach

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I am building this clock gating cell using standard cells from FreePDK45. However, what is wrong with XOR2 (I44) ?

 

BradtheRad

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XOR2 has its 'A' input wire lit up blue so it's hard to be sure the simulator recognizes if it has a proper connection to the wire between 2 red dots. Does the simulator turn joins red? That creates a question about the blue dots, whether it's a proper join.
 

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