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Questions on set_output_delay

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promach

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1. For set_output_delay command, why the maximum output delay value should be equal to the length of the longest path to the register data pin, plus the setup time of the register ? Why the minimum output delay value should be equal to the length of the shortest path to the register data pin, minus the hold time ?

2. I do not understand why To model a later output data arrival time you must therefore decrease the output delay amount. ?

Included External Clock Latencies.png
 
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