set_clock_gating_check questions

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promach

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I have two questions below for set_clock_gating_check command which is also highlighted in yellow below:

1. Why for OR and NOR gates, the setup check is performed with respect to the falling edge of the clock input ?
2. Why for OR gates, the non-controlling value is low ?





 
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answering the second question:
if you OR something with zero, you always get something. this is why we say the non-controlling value of an OR gate is zero.
 

I think the document is referring to non-controlling value of CLOCK
 

promach said:
I think the document is referring to non-controlling value of CLOCK
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still zero. look at the schematic. you can call the clock signal banana123 or whatever, the noncontrollling value is still zero.

what am i missing?
 

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