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ami said:select an A value for input/output ( A can be negative/positive, depends on the number of logics at your input/output)
----> for output
outut_delay < C - U -2 - A
----> for input
input_delay < 2 + A
----> max_path_delay from output to input of your 2 module
= (C-U-2-A) + (2+A) = C-U
------------------------------------------
hope this help.
An input delay is the specification of an arrival time at an input port relative to a clock edge.The path length from the clock pin of the source flip-flop to the output pin of the driving cell,minus the load-dependent portion of the driving cell’s delay should be equal to the input delay.
An output delay describes an external timing path from an output or inout port to an external register. To describe this path correctly the maximum output delay value should be equal to the length of the longest path to the register data pin, plus the setup time of the register. Also the minimumoutput delay value should be equal to the length of the shortest path to the register data pin,minus the hold time.