Relationship between tracks and delay

[Cya]

In the physical design we use 6T, 7.5T, 9T etc. It's said that higher the track faster the cell is. How are track and speed of a cell related to each other?

Thanks in advance!

 

[oratie]

Higher track -> bigger transistor (bigger gate width) -> faster transistor.

 

[ThisIsNotSam]

Higher track -> bigger transistor (bigger gate width) -> faster transistor.

That is how it works for a single cell in isolation, but there are more factors. I hope OP can follow this:
- bigger cells means more area which means more routing which means more capacitance which means slow down.
- bigger cells are also a bigger (pin) load for cell that comes before them. this can have an impact too. but they drive more, which can compensate.
- ... but bigger cells have more routing tracks too, which can help with congestion and give back some of the loss due to size.

there are many many things to consider. channel size matters too. chip size matters. metal stack matters. this is why std cell providers will give you options. the best option for one block might not be the best option for another block.