Set max delay constraint

[anjali]

set max delay

Can we use set max delay to constraint synchronous designs. Is it advisable?

 

[ami]

maxdelay constraint


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set_max_delay defines the maximum delay required in terms of time units for a
particular path. In general it is used for blocks that contain combination logic only.
However it may also be used to constrain a block that is driven by multiple clocks, each with a different frequency.


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[anjali]

max delay

thanks for your reply.

Let 2 modules r driven with a same clk. then shall we use set_max_delay to constrain the path delay between those modules. is it advisable?

 

[ami]

set output delay

the set_input_delay and set_output_delay constraints are enough in this case,
and remember that you should add the same trace-delay into the input/output delay like below

Assuming that:
your clock cycle = C(ns)
clock Uncertainty = U (ns)
your trace-delay + other = 2(ns) ( depends on the distance between 2 modules)

select an A value for input/output ( A can be negative/positive, depends on the number of logics at your input/output)

----> for output
outut_delay < C - U -2 - A

----> for input
input_delay < 2 + A


----> max_path_delay from output to input of your 2 module
= (C-U-2-A) + (2+A) = C-U

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hope this help.

 

[aravind]

maxdelay

can u please explain more about trace-delay

and how u acheive this equation
your trace-delay + other = 2(ns) ( depends on the distance between 2 modules)


please if u have any paper share here

 

[anjali]

set_max_delay synchronous clocks

select an A value for input/output ( A can be negative/positive, depends on the number of logics at your input/output)

----> for output
outut_delay < C - U -2 - A

----> for input
input_delay < 2 + A


----> max_path_delay from output to input of your 2 module
= (C-U-2-A) + (2+A) = C-U

------------------------------------------
hope this help.

how do you select value A. you r saying that A depends on logic at input or output.
and you r comparing output&input delays with A.

 

[ami]

max delay constraint

*To aravind
The trace delay + other is the reserved timing for P&R( depends on the size & condensed of your design and on the distance between 2 modules on the die). I think 2ns (my experience) is OK in many case.

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*To anjali
The A value depends on your design rule.(for all general cases)
For an example: all output must be from register(output_delay max) when there allow some logics to be put at inputs. --> "A" delay is reserved for input (positive),
ex:
C = 6.4
U = 0.4
output delay = max = 6 = 6.4 - 0.4 - 2 - A
---> A = -2
input delay = 2 + (-2) = 0

*****************
----------> you can see from this case that
1. max path timing is 6ns (from an output to an input)
2. with A value, the constraints will test and find any input/output does not meet your design rule


-----------> if you dont have a design rule like that, I think it is difficult to use my idea.

Regards

 

[aravind]

what is set_max_delay

for setting Design rule constraint like max_transition time and wireload models
we need to read library
can u explain more about user define constraints andfor what constraints we must have to read library
if u have any examples code and constraints it is usefull

 

[ami]

max delay constraints

An input delay is the specification of an arrival time at an input port relative to a clock edge.The path length from the clock pin of the source flip-flop to the output pin of the driving cell,minus the load-dependent portion of the driving cell’s delay should be equal to the input delay.

An output delay describes an external timing path from an output or inout port to an external register. To describe this path correctly the maximum output delay value should be equal to the length of the longest path to the register data pin, plus the setup time of the register. Also the minimumoutput delay value should be equal to the length of the shortest path to the register data pin,minus the hold time.