hosseineslahi7
Junior Member level 1
Hi All,
I have designed a 4 bit DAC for biasing a neuron. I have some questions regarding the performance of my DAC.
The post-layout simulations show INL and DNL lower than 0.16LSB. First, do they depend on the sampling rate or speed of the DAC? Second, what is the definition of the sampling rate or speed of a DAC and how can I determine these parameters in my design? Is there a way to calculate the speed of the DAC?
I appreciate it if you guys help me in this regard.
Cheers,
Hossein
I have designed a 4 bit DAC for biasing a neuron. I have some questions regarding the performance of my DAC.
The post-layout simulations show INL and DNL lower than 0.16LSB. First, do they depend on the sampling rate or speed of the DAC? Second, what is the definition of the sampling rate or speed of a DAC and how can I determine these parameters in my design? Is there a way to calculate the speed of the DAC?
I appreciate it if you guys help me in this regard.
Cheers,
Hossein