Sampling rate, delay, and the speed of a DAC

[hosseineslahi7]

Hi All,
I have designed a 4 bit DAC for biasing a neuron. I have some questions regarding the performance of my DAC.
The post-layout simulations show INL and DNL lower than 0.16LSB. First, do they depend on the sampling rate or speed of the DAC? Second, what is the definition of the sampling rate or speed of a DAC and how can I determine these parameters in my design? Is there a way to calculate the speed of the DAC?

I appreciate it if you guys help me in this regard.

Cheers,
Hossein

 

[sutapanaki]

INL and DNL are DC characteristics both for DAC and ADC. They are measured at low speed, when everything in the DAC has settled.
Sampling rate of the dac is defined by the rate at which your input date comes in. DAC by itself does not sample, it receives samples from whatever digital is driving it. Speed is usually something related to the minimum time required for the DAC output to settle to within the required precision. So, DA has to settle for the time between two input samples.

 

[KlausST]

Hi,

I agree.
Besides this... almost every DAC manufacturer provides a lot of documentation about DAC parameters.
They are free, made for you, so use them.
You will hardly find more reliable and more detailed information.

Klaus

 

[hosseineslahi7]

INL and DNL are DC characteristics both for DAC and ADC. They are measured at low speed, when everything in the DAC has settled.
Sampling rate of the dac is defined by the rate at which your input date comes in. DAC by itself does not sample, it receives samples from whatever digital is driving it. Speed is usually something related to the minimum time required for the DAC output to settle to within the required precision. So, DA has to settle for the time between two input samples.

Hi Sutapanaki,
Thank you for your answer. Based on what you said, I have to look at the output characteristic of my design and find the settling time of my design. Am I right? Is it the time required for DAC to jump from one level to the next level (one LSB difference between two consequent steps)?

Is there any other way to calculate the delay (or settling time) mathematically? I mean, maybe I need to compare the theoretical calculation to the simulation results for settling time.

Regards
Hossein

--- Updated Aug 29, 2021 ---

INL and DNL are DC characteristics both for DAC and ADC. They are measured at low speed, when everything in the DAC has settled.
Sampling rate of the dac is defined by the rate at which your input date comes in. DAC by itself does not sample, it receives samples from whatever digital is driving it. Speed is usually something related to the minimum time required for the DAC output to settle to within the required precision. So, DA has to settle for the time between two input samples.

In addition, is the conversion frequency or conversion rate of the DAC calculated by 1/(settling time)?

 

[sutapanaki]

Well, you know best your design and I am sure you can figure out if there is another mathematical way to calculate the delay.
Yes, you have to look at the output characteristic of your DAC for every parameter you are interested in. For the delay, usually the worst case is going from minimum code to the max code and look how much time it takes for the output to settle within 0.5LSB of the DAC.
Conversion rate is the rate at which the samples arrive to your DAC. Max settling time within the predefined precision will define your max conversion rate obviously. This being said, you have to be aware that there are other DAC parameters that you may or may not be interested in. Like distortion for example which will also be dependent on the conversion speed and on the INL/DNL.

 

[hosseineslahi7]

Hi Sutapanaki,
Thank you for your support. Everything is clear now.

Regards