surisingh
Member level 1
Hi,
I have one SV file where I have to include it in multiple System verilog test cases. Obviously, I will be receiving compilation errors..
Say I have declared a parameter in the include file.. For the first test case, I'll not get any compilation error; when the compiler compiles the second
test case and when it compiles the same include file, it obviously reports error saying that the parameter already declared..
How can I overcome this with efficient SV construct?
Thanks
Suresh
I have one SV file where I have to include it in multiple System verilog test cases. Obviously, I will be receiving compilation errors..
Say I have declared a parameter in the include file.. For the first test case, I'll not get any compilation error; when the compiler compiles the second
test case and when it compiles the same include file, it obviously reports error saying that the parameter already declared..
How can I overcome this with efficient SV construct?
Thanks
Suresh