[SOLVED]Same include file in multiple SV test case!!!

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surisingh

Member level 1
Hi,

I have one SV file where I have to include it in multiple System verilog test cases. Obviously, I will be receiving compilation errors..
Say I have declared a parameter in the include file.. For the first test case, I'll not get any compilation error; when the compiler compiles the second
test case and when it compiles the same include file, it obviously reports error saying that the parameter already declared..

How can I overcome this with efficient SV construct?

Thanks
Suresh

kingslayer

Member level 4
Hi,

Code:
// In myHeader.h
'ifndef _DUMMY_
'define _DUMMY_

// any common declaration here

'endif

In this way, the first time the compiler tries to compile the declarations, it will since the _DUMMY_ preprocessor variable is not defined. The second time it won't, but the declaration will be still there at your disposal!

Cheers

surisingh

Member level 1
Thank you. It was my bad.. It should work.. I don't know how I forgot this...

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