regarding timing convergence

[moorthy]

hi
i am doing project on "TIMING CONVERGENCE".. i need the materials regarding timing convergence.. please share with me..

thanks in advance..
regards
moorthy

 

[ljxpjpjljx]

Your research is regarding timing analysis in Analog or Digital?

 

[vlsichipdesigner]

hi,

my 2 cents,

what do you mean by timing convergence, is it timing corelation?

* how to model wireload models and achieve better correlation and a faster timing convergence after p&r stage.
* how to model the onchip variations and what are the various variations to account for and how much percentage to apply and achieve timing convergence between pre-silicon and post-silicon activities.
* timing convergence when we use different tools
* how to achieve faster timing closure, whether do we need to take STA as a golden rule or SSTA(Statistical STA ) as a golden rule to attain timing convergence.
* how to measure the accuracy of the models being used to model timing like QTM/ETM/ILM and other models if any due to various reasons, hierarchical, run-time reduction, multi-tasking and how to bet against their accuracy and claim timing convergence.
* how many modes do we run the chip say in functional, in test modes how to create such a Multi mode multi corner scenarios from the start of the flow and finally achieve timing convergence during final stage.
* how many corners or modes do i run like normal, ocv, ocv si, aocv , aocv si max and min for all the modes and achieve timing convergence.
* how do apply derates during the start of the flow itself to say that i will model on chip variation, and meet timign when i come to the final stages.

there are thousands queries,.....
myprayers,
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