regarding layout in cadence virtuoso

[muraleedharapatro]

hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....


THANX IN ADVANCE.

RAGARDS
MURALEE.

 

[em1cr0nix]

hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....


THANX IN ADVANCE.

RAGARDS
MURALEE.

i have not experienced using assura yet but it is most likely referring to the distance between the P and N devices. try to increase the distance (20um as indicated in the error result) between the N and P device, as well as its taps (guardring) to remove the error.

 

[deepak242003]

hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....


THANX IN ADVANCE.

RAGARDS
MURALEE.

IT is indicating latchup error.
You might have not added tap connection for NMOS.. give p tap and connect to ground and this error willl be gone

 

[protonixs]

hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....


THANX IN ADVANCE.

RAGARDS
MURALEE.

put your ptap as close as possible to the n-type device. in your case, the ptap is placed more than 20um away from the n-type device.

 

[shashikumar.22]

put ptab connection or either a ring of ptab to NMOS which should be connected to ground.

 

[muraleedharapatro]

thanx a lot to all ur replies...

@deepak

i m at layout part..i didnt get ur answer,can u plz tel me how to do this.

regards
MURALEE.

 

[deepak242003]

i m at layout part..i didnt get ur answer,can u plz tel me how to do this.

regards
MURALEE.

You can surround your NMOS wiht substrate guard ring and connect it to VSS or lowest analog potential..

Dont forget to press HELP ME Button...

 

[protonixs]

i m at layout part..i didnt get ur answer,can u plz tel me how to do this.

regards
MURALEE.

You can surround your NMOS wiht substrate guard ring and connect it to VSS or lowest analog potential..

Dont forget to press HELP ME Button...

no matter how you put many guardrings if it is not close to the device (should be less than 20um in your case), the error will not be corrected.

 

[dipak.rf]

You can surround your NMOS wiht substrate guard ring and connect it to VSS or lowest analog potential..

Dont forget to press HELP ME Button...

It doesnt matter if you surround ur NMOS full with guardring and connect to VSS, its the error looking for two PWELL contacts atleast 20um space each other, it means you have to keep PWELL contacts or guardring minimum 20 um in ur case space between each not more than that (obviously it connect to VSS or low potential), so check all ur NMOS for substrate connection spacing

 

[prakashreddy]

add sustrate(nmos tie) to the nmos ,or press o in key board, and pick m1_psub ,place near to the nmos.

 

[dipak.rf]

add sustrate(nmos tie) to the nmos ,or press o in key board, and pick m1_psub ,place near to the nmos.

Ya i agree; you can do this if you have more spacing or not sharing NMOS in one matching geometry. for each NMOS to take M1-psub which connects to VSS