hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....
hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....
i have not experienced using assura yet but it is most likely referring to the distance between the P and N devices. try to increase the distance (20um as indicated in the error result) between the N and P device, as well as its taps (guardring) to remove the error.
hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....
hi all..
I am doing layout in cadence virtuoso tool.
When i run ASSURA DRC(Design rule checking) to debug the errors its showing one
error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um.
Its indicating at every NMOS in the design.
I am unable to clear this one.
plz help me out .....
It doesnt matter if you surround ur NMOS full with guardring and connect to VSS, its the error looking for two PWELL contacts atleast 20um space each other, it means you have to keep PWELL contacts or guardring minimum 20 um in ur case space between each not more than that (obviously it connect to VSS or low potential), so check all ur NMOS for substrate connection spacing