Reason for putting the JTAG cell as close to IO pad as possible

[leeenghan]

Hi,

In P&R, the JTAG (boundary) cells are always placed as close as possible to the I/O pad. This make sense as the JTAG cell are connected to the pad.

My question is beside connectivity requirement, is there other requirement that make it important to place the JTAG cell as close to the IO pad as possible? Is there timing consideration, or something else?

Thanks.

Regards,
Eng Han

 

[luancao]

Re: P&R of JTAG Cell

Let's figure out the structure of the JTAG related thing. The path to the logic includes pad, io cell and bsr cell. So additional input delay and output delay are introduced. The paths to IO are often critical paths when you are doing a timing analysis.

Put the BSR cell near the correspondent IO also makes the BSR chain connected one by one. of course, the performance of the JTAG raised to some extend. But the JTAG is very slow port, timing is not a problem in JTAG.

Whatever, put the pad, io cell, bsr cell together is the most convenient way. What else can we do if we don't layout like that?

 

[leeenghan]

Re: P&R of JTAG Cell

Hi Luancao,

I agree that there are timing and connectivity concern, and so it is best to put them close to the pad.

What I did not understand is why must they be as close to the pad as possible, even if timing can be met, and routing to the pad is not a problem. Assume that there are big macros that block many of the pads, should I leave a gap in-between the macro and the pad to place the JTAG cells? This can be done, but the clock latency to the JTAG cell will be creating trouble.

Regards,
Eng Han

 

[luancao]

Re: P&R of JTAG Cell

Hi, Eng,

For JTAG, mainly two parts, one is JTAG controller, the other is BSR cell. BSR cell should be close to IO cell. JTAG controller could be put anywhere convenient for you.

If there is big macro there you could aslo layout in that way since BSR cell is very small comparing with the IO cell (at most two registers). So almost no "gap" in between. Of course, physical designer have to be involved and sometimes it has to be done by hand. Usually if we use a unified naming convention the BSR cell could be find easily. You could get it done at the same time when you layout the IO cell. In my past work, we put all the IO in a module in RTL and BSR cell in a module. Therefore in the hierachy netlist you could find the correspond IO and BSR easily.

However, all these conventions are for the timing and connection. If you are sure there is no timing and connection issue and area is also not your concerning. Let it be. But who knows? What if you meet a connection problem in the halfway or your timing check could not pass after you get a final layout?

 

[ms2004]

Re: P&R of JTAG Cell

Hi,

There are many more things should be taken care while P&R of the JTAG cells. Everyone says that JTAG timing is not very critical, and i dont agree with that one. Most of the board testing people use this JTAG for onboard debug. And there are many chips sitting on board, it this specific chip does not run JTAG bscan fast enough as compared to other chips, this chip can be classified as bottleneck.

For a better placement and timing requirement, we have made a small hard macro of this bcell, and it was easy to place, no worries.

Also designer has to be clever enough to make sure that bcell control signal are flowing in one direction and clock is flowing in other direction. Since this bcell logic is around the periphery of the chip, it is difficult to balance the skew.

-> Control Signal -> bcell -> bcell -> control signal
<- clock signal <bcell <- bcell <- clock signal

-Milind Sonawane