questions about high-speed comparator design

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mayongwangblg

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Hi

i want to design a comparator with a propagation delay of less than 1ns, and a precision of 10bit.

is that possible by using 0.18umCMOS technology? or i have to use a better technology like SiGe-BiCMOS?

Thanks for your help!
 

Hi

what your LSB will be, and what sigma are you talking about.
I think it would be feasible if you use digital calibration techniques.
 

1LSB<2mV, is it possible?

and i have another question,
what is the relationship between "propagation delay" and "bandwidth"?

thanks for your help.
 

the term "precision" in relation to comparator is uncertain,- better to define sensitivity level for given delay/speed, and maximum offset value. For some type of ADC (e.g. SAR) offset doesn't limit ADC's resolution. The term "bandwidth" for comparator also don't clear define it's speed,- contrary to OAs it can incorporate many stages (>>2) and don't require to be stable in close loop configuration. Sensitivity better 1mV with delay <1ns is realistic target for 0.18um node, but offset <1mV isn't without experience, I think.
 

I'll have to agree with mikersia, the offset is the difficult parameter here.
What kind of ADC architecture you want to implement?

About the propagation delay, here is a very simplistic way (might be wrong, do an RC circuit and compare the results).

For a single pole circuit (Prop.Delay) Tpd = 0.7RC.
Also (pole frequency) Fp = 1/(2*pi*R*C).
So to achieve 1ns Tpd you need an RC = 1.428ns which translates to Fp = 1/(2*pi*1.428E-9) => Fp = 111Mhz.

This is an easy target, but some other specifications might need a higher bandwidth (SFDR of the ADC for example)
 

The above single pole analysis is right.
This is with an RC=1.428ns [R=1.428Kohm, C=1pF]

 

thank you, lamoun and mikersia.
it is the analysis for a single-pole system, but what is the relationship between Tpd and -3dB bandwidth for a multi-pole system?
is it the same with single-pole system?
 

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