Gate driver circuit design for High-side and Low-side

[aguntukbd]

I am designing integrated DC-DC converter with multiple output. As I am new to Analog design, I am trying to figure out what type of circuit topology is to be used for high-side and low-side switches. High-side is a pmos and lowside is a nmos switch. I am using 22nm technology with typical Li-ion battery input voltage (2.5V to 4.1V range, nominal 3.7V).

I am using 22nm technology. Though for the high-side and low-side I will try with LDMOS. I am just not sure which topology to use from the PWM output to the LDMOS for driving the gate. What I mean, I am looking for gate driver circuit. Googling give me mostly to use gate driver ic to use which is not my intention. I want to start with common gate driver topology to start with. I figured my peak current required and switching frequency as well. I also sized preliminarily my LDMOS with current requirement. I need to drive the mosfet now from digital PWM. So I have to drive the MOSFET to design a circuit between the DPWM and the pmos /nmos as well and as well as nmos and other switches. Now for PMOS I selected the lowest voltage of Li-ion battery 2.5V and input pwm voltage would be 1.8V during its ON-duty cycle. Can anyone suggest what type of circuit should I use to drive the gates of the switches, specially pmos?

 

[dick_freebird]

If you mean to integrate the power switches, and both operate between
the primary negative and positive rails, then you don't really have a
driver other than the taper-chain and anti-shoot-through. 5V POL DC-DCs
are that way (although in the interest of compact die size, NMOS high side
is often a "better deal" aside from requiring the customer to add a bootstrap
capacitor to their BOM).

I find your description of various voltages and actions unclear / messy.
I think some time spent block by block, from the outside in, would help
you make sense of things (rather than collecting random nuggets of
Internet advice).

As an example - you know the load and the edge dV/dt you want, to
support the fSW and overlap interests, right? So now you can size the
final NMOS and PMOS. And from there, size the last predriver stage to
not-degrade (4 devices, with ideal gate drive phasing to make-so the
slew and nonoverlap. Then the eightt devices (4 pairs) preceding...

It's all just a big dumb inverter, real big. Until you start adding stuff
like anti-shoot-through (servo or ballistic), output behavior in shutdown
and current sensing, anyway. Which all had best be on the table from
the start, as otherwise you'll be taking another lap around that obstacle
course.

 

[BradtheRad]

Now or later you must give some time to exploring the behavior of transistors:

* whether to choose N-device or P-device to be more effective in a location,

* range of bias voltage that yields turn-On or shut-Off at proper moments,

* whether you need to build an independent clock to provide bias, or whether you can tap for bias automatically at proper moments somewhere in the circuit,

* whether or what sort of bootstrap circuit is needed for N-device in high side,

* whether you can control two transistors (an N-device and a P-device) with one bias signal.