blueagate
Member level 1
preliminary scanning ullman compiler design
I want to inset scan from RTL code.
The script I had written is here:
analyze -f verilog top.v
elaborate top
some constrains here ...
set_scan_configuration -style multiplexed_flip_flop
crete_test_clock -period 100 -waveform {0 50} clk #clk is a port in the RTL code
set_test_hold 1 scan_mode
set_scan_signal test_scan_enable -port scan_en
set_scan_signal test_scan_in -port test_in
set_scan_signal test_scan_out -port test_out
check_test
compile -scan
insert_scan
check_test
I recieve the information from Design Compiler:
Warning: Can't find port 'scan_mode' in design 'top'
Warning: Can't find port 'scan_en' in design 'top'
Warning: Can't find object 'test_in' in design 'top'
Warning: Can't find object 'test_out' in design 'top'
This is the first time I added scan in the design,
I had not add these port in the design top,
I thought that Design Compiler would add thest ports automatically.
Does anyone can tell me how to add these ports in the RTL code or script?
Thanks.
I want to inset scan from RTL code.
The script I had written is here:
analyze -f verilog top.v
elaborate top
some constrains here ...
set_scan_configuration -style multiplexed_flip_flop
crete_test_clock -period 100 -waveform {0 50} clk #clk is a port in the RTL code
set_test_hold 1 scan_mode
set_scan_signal test_scan_enable -port scan_en
set_scan_signal test_scan_in -port test_in
set_scan_signal test_scan_out -port test_out
check_test
compile -scan
insert_scan
check_test
I recieve the information from Design Compiler:
Warning: Can't find port 'scan_mode' in design 'top'
Warning: Can't find port 'scan_en' in design 'top'
Warning: Can't find object 'test_in' in design 'top'
Warning: Can't find object 'test_out' in design 'top'
This is the first time I added scan in the design,
I had not add these port in the design top,
I thought that Design Compiler would add thest ports automatically.
Does anyone can tell me how to add these ports in the RTL code or script?
Thanks.