Question about scan insert using Design Compiler

[blueagate]

preliminary scanning ullman compiler design

I want to inset scan from RTL code.
The script I had written is here:

analyze -f verilog top.v
elaborate top

some constrains here ...

set_scan_configuration -style multiplexed_flip_flop
crete_test_clock -period 100 -waveform {0 50} clk #clk is a port in the RTL code
set_test_hold 1 scan_mode
set_scan_signal test_scan_enable -port scan_en
set_scan_signal test_scan_in -port test_in
set_scan_signal test_scan_out -port test_out
check_test
compile -scan
insert_scan
check_test

I recieve the information from Design Compiler:

Warning: Can't find port 'scan_mode' in design 'top'
Warning: Can't find port 'scan_en' in design 'top'
Warning: Can't find object 'test_in' in design 'top'
Warning: Can't find object 'test_out' in design 'top'

This is the first time I added scan in the design,
I had not add these port in the design top,
I thought that Design Compiler would add thest ports automatically.

Does anyone can tell me how to add these ports in the RTL code or script?

Thanks.

 

[elektor]

insert_scan insert_dft

First at all,
You have to create test clock, but different manner :
for example:
create_test_clock clock -period 100 -w {30 70}

above you can also insert :
test_stil_netlist_format = verilog
test_default_delay = 0
test_default_bidir_delay = 0
test_default_strobe = 20
test_default_period = 100

Easy when you add scan_en in your top design and scan_in , scan_out you relate with real ports in design .
For example :
set_scan_signal test_scan_in -port <real port>

Regards
Elektor

 

[horzonbluz]

set_scan_signal site:edaboard.com

Hi, my friends.
I suggest you should not insert scan chains in RTL codes.
You must know that test clocks are usually slow than normal clocks. So we just use scan cell in RTL codes compiler, then insert scan chains in DFT.
In DC:
compile -scan;
compile -effort high -inc
In DFT, you can insert_scan or insert_dft.
test_default_strobe = 20 # Don't set this for protocol, this will occur a fatal error.

 

[elektor]

test_default_strobe in dft

Hi,
In my post I do not suggest insert scan chains in RTL codes but only empty port scan_en. This port DFT Compiler will use for scan enabling.

Horzonbluz - Could you explain why "test_default_strobe = 20 will occur a fatal error" and where ?

Regards:
Elektor

 

[haosg]

design compiler scan insertion

you can create scan_en port directly in DC,
create_port scan_en.
and if you don't assing port to scan-in and scan_out, DFTC would
automatically create them.
however you can assign a functional port for scan-in and scan-out.

 

[blueagate]

design compiler how to compile with scan

Hi, my friends

I added the port scan_en at the top module,
and I wrote the script:

set_scan_configuration -style multiplexed_flip_flop
crete_test_clock -period 100 -waveform {0 50} clk #clk is a port in the RTL code
set_scan_signal test_scan_enable -port scan_en
check_test
compile -scan
insert_scan
check_test


I did not add the scan input/output port, after compiled DC added port test_si and port test_so
automatically.

Thanks for your advice.

But there is another problem,
I don't know what this script means,

"set_signal_type test_asynch_inverted rst"

rst is the reset signal in my design, which active low,

I can't see any difference between adding this sentence and without it.

P.S. the design my testing is tiny, total 33 flip-flop in it.

Haha,
Can someone tell me the difference between "insert_scan" and "insert_dft"?

 

[horzonbluz]

how to insert scan chain

"set_signal_type test_asynch_inverted rst"
This setting sets your reset signal rst is a asynchronous reset signal and hold constant 1 value in DFT.
When your design is test ready state and no scan chains in your design, you can use insert_scan to insert scan chains. If your design contains some IPs that have been inserted scan chains, you can use insert_scan in top module.