Problem with function and timing in PAD

[qjlsy]

pad, timing, function???

If clk(generated in tb) propagates into chip through such kind of PAD, it seems to get wrong timing which will lead to function failed.

-------------------------------------------------------------------
module PADX;
input ...
output ...

buf (...);
bufif0 (...);

specify block: all timing definitions equal to 0.

endmodule
-------------------------------------------------------------------

But if to drive clk into chip directly from clk generated in tb, every thing is right & function meets.

No timing difference can be detected in waveform between clk signals before & after the pad. And the pad just uses buf-class gates. So I am very curious about how such pad influence timging or function. :?:

Could anybody give me some help? Thanks a lot!

 

[xigu]

pad, timing, function???

I think the important in RTL simulation is logic verification. Without the accurate model, the timing check is rough.

Also PAD timing need be considered in synthesis constrain, i.e. input_delay...

In final we check function and timing in simulation with SDF files.

BE do PAD and clock tree work.

 

[qjlsy]

Re: pad, timing, function???

Agree with you:

"Without the accurate model, the timing check is rough.

Also PAD timing need be considered in synthesis constrain, i.e. input_delay...

In final we check function and timing in simulation with SDF files. " -- it is the traditional post-simulation.
------------------------------------------------------------------------------------
BUT

Here what I want to do is functional verification. I want to verify the function of the entire chip which use pads as the outside interfaces.

The code is a verilog model for PAD from foundry. And I also opened "notimingchek" option in simulation.

Timing error I said is the estimation of myself. Because when I replaced clk pad with a wire, every thing works right. If I didn't do such replace, no clk skew found from waveform, but the stimulus generated in testbench seemed to change earlier than clk in chip, which cause a functional error.

I am confused. Could anybody help me? Thanks a lot!

 

[kermit]

Re: pad, timing, function???

Without the accurate model, the timing check is rough.

Also PAD timing need be considered in synthesis constrain, i.e. input_delay...

In final we check function and timing in simulation with SDF files.

I faced this problem too.Because I didnt have plenty of time to inspect this , I just replace a simple wire to replace the buffer.Then the full work well.
Ya,this question is very interesting !!!

 

[skymusic]

pad, timing, function???

If no sdf back-annotated or specify, the simulator do not know the delay value, we can not see the delay in buf or other gates. Use synthesis tools or P&R tools, can extract sdf file to simulate.

 

[qjlsy]

Re: pad, timing, function???

I want to do functional verification, not post simulation. And I also used notimingcheck option, even though the buf delay in model is zero.

Is there any other suggestion or explanation? Thanks!

 

[rol73]

Re: pad, timing, function???

With notimingcheck option, you've deactivated timing checks on internal gates (i.e. setup, hold, ..), but the buffer effect still remains: your clock enters the chip a delta later than using a simple wire... you could verify if any path from stimuli (other than clock) have same length than clock itself (with PAD)...

I hope this could be useful for you...

 

[qjlsy]

Re: pad, timing, function???

Dear rol73,

"you could verify if any path from stimuli (other than clock) have same length than clock itself (with PAD)... " ????

Do you mean that I need to check the path length of clock (from testbench clk generation output to clk pad output) & that of other stimuli, take "d_in" as example(from behavior model "d_in" to WHERE?)? And compare them to see they are the same or not? ???

But path length from testbench need not be considered as they are not part of rtl, which is the final design.

I think I don't catch you. So would you please give a more detail demonstration? Thanks a lot!

By the way, you said "your clock enters the chip a delta later than using a simple wire". This is the real effect of buffer. But from the behavior model of the pad code, it can be seen that the delays in specify block are all set to zero, and from the dump waveform the delta difference between internal clock and other input (with pad too) cannot be seen.

Could you give me more help? Thanks a lot!

Best Regards,

qjlsy