Problem with Design Compiler an tetramax

[danilo]

Hi

I mada a synthesys with design Compiler and the process ends without error.
I saved the netlist in verilog format.
I try to read this netlist with Tetramax, but the bus / wire contention ability check fails due to a wire gate.
The error is

Error: Wire gate (997) failed contention ability check for drivers 994 and 996. (Z3-1)

Any suggestion?

Thanks a lot in advance