My design is I2C slave circuit, it latch data by pos-edge of SCL and output by neg-edge of SCL. I run simulation post-synthesis with Modelsim, it is ok. And then I generate cdl file from nestlist with CMOS models, but when I run simulation with HSPICE, it is wrong.
When it send ACK bit , SDA change low to high at post-edge. So the circuit can not work. I dont know what problem with the circuit. Please help me.
The analysis should allow to recognize, why the circuit is failing, respectively which logic cell is behaving different from ModelSim analysis. Because of the required dual-edge sensitivity, the circuit has to be designed as a combination of synchronous and asynchronous logic. There are many possible traps in this kind of design.
You can design a logic with a dual-edge, the ModelSim don't cry about it but it is then sure non-synthesizable.
Use just one clock, for example negedge SCL, and design some asynchronous logic [with "assign" statement, if I remember correctly...] which generates the other synchronization possibilities, if you need them.