Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

I2C Slave - filters and clock.

Status
Not open for further replies.

Liffs

Member level 1
Joined
Mar 7, 2012
Messages
32
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,288
Location
Brazil
Activity points
1,472
I want to implement a I2C SLAVE in an FPGA, just for learning purposes. I read in the I2C specification that for the FAST mode there is a timing parameter tSP = 50ns (max) which means "pulse width of spikes that must be suppressed by the input filter". Should this be a digital filter inside the slave? If yes, does that mean my slave must have a maximum clock period of 25ns (or something)?

Another question would be: is there a (robust) way of implementing this slave using the SCL line as the only clock? Or a faster second clock is needed (and in this case I would treat the SCL line as "data")? If so, how do I calculate the minimum frequency of this other clock?

Thanks in advance!
 
Last edited:

I don't think you want to put a digital filter on a simple I2C interface; just an RC and proper design should suffice. And, if this is just for learning purposes, I wouldn't even worry about filtering out spikes that may not even exist.

I SUPPOSE you could use SCL as your main clock, but I wouldn't. That puts you at the mercy of whatever is driving SCL. If that device fails, your whole system fails.
 
  • Like
Reactions: Liffs

    Liffs

    Points: 2
    Helpful Answer Positive Rating
A full featured I2C slave supports clock stretching and implements SCL as bidirectional signal, surely not data. Even a simplified slave performs actions on SCL and SDA edges and can't use SCL as clock.

Most slave implementations on complex devices uses synchronous logic with overclocking, simple devices have asynchronous logic.
 
  • Like
Reactions: Liffs

    Liffs

    Points: 2
    Helpful Answer Positive Rating
A full featured I2C slave supports clock stretching and implements SCL as bidirectional signal, surely not data.
Hi! Thanks! Why do you mean by "surely not data"?
--- Updated ---

Most slave implementations on complex devices uses synchronous logic with overclocking, simple devices have asynchronous logic.
By asynchronous logic do you mean I2C slaves without a clock at all? Can't imagine...
 
Last edited:

Hi! Thanks! Why do you mean by "surely not data"?
My fault, just confused. Commenting your post #1, I meant to say surely data not clock.
By asynchronous logic do you mean I2C slaves without a clock at all? Can't imagine...
Presume simple peripherals, e.g. I2C port expanders are implemented this way.
 
  • Like
Reactions: Liffs

    Liffs

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top