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# How to estimate roughly the valid clock frequency?

#### coshy

##### Member level 4
I have a signal with a WNS of 30ns after synthesis on an FPGA with a clock of 16MHZ.
What is the maximum clock that can offset the 30ns WNS?

Considering the WNS 30ns at the current 16Mhz clock, how do I calculate and what is the maximum effective frequency I can expect to offset the WNS 30ns roughly? It will probably be less than 16Mhz, but how do you calculate it? If an exact calculation is not possible, I would like to know how to get a rough estimate.

I have a signal with a WNS of 30ns after synthesis on an FPGA with a clock of 16MHZ.
What is the maximum clock that can offset the 30ns WNS?

Considering the WNS 30ns at the current 16Mhz clock, how do I calculate and what is the maximum effective frequency I can expect to offset the WNS 30ns roughly? It will probably be less than 16Mhz, but how do you calculate it? If an exact calculation is not possible, I would like to know how to get a rough estimate.
Your negative slack is too high. If I assume it is setup slack then I can make a guess:
1000/16MHz = 62.5 ns clock period
invert back to frequency: 1000/92.5 = 10.8MHz

Without even the calculations, if you understand what Slack is, it is possible to rouglhly estimate.
Clk period is 62.5 ns, and NSlack is 30 ns, which is bit less than 50% of the period.
Hence the max clock frequency will be a bit more than half the freq of 16MHz.
So I would estinate it to be >8 MHz, so 10MHz is a good estimate.

But the above post shows how to calculate it and you should follow it!

There is a caveat in the calculations... just because you have a negative slack of 30ns, does not mean that the best possible period is clk period + WNS. Once you come up with a more reasonable clock period, the synthesis toll will work on a different regime and might be able to do a better job. It is all about heuristics.

There is a caveat in the calculations... just because you have a negative slack of 30ns, does not mean that the best possible period is clk period + WNS. Once you come up with a more reasonable clock period, the synthesis toll will work on a different regime and might be able to do a better job. It is all about heuristics.
of course, every build means a different Place & Route especially so if clock speed is changed. It is just a guess calculation specific to the question in case the OP wants to use lower clock speed on same build.
The relation of slack and clock speed is relevant to setup (not hold, which occurs if clock delay is more than data delay even at low clock speed, commonly happens with beginners gating the clock).