ise_lewis
Newbie level 3
My design is I2C slave circuit, it latch data by pos-edge of SCL and output by neg-edge of SCL. I run simulation post-synthesis with Modelsim, it is ok. And then I generate cdl file from nestlist with CMOS models, but when I run simulation with HSPICE, it is wrong.
When it send ACK bit , SDA change low to high at post-edge. So the circuit can not work. I dont know what problem with the circuit. Please help me.
When it send ACK bit , SDA change low to high at post-edge. So the circuit can not work. I dont know what problem with the circuit. Please help me.