Hi, all
I am designing a LDO. But when I simulated the open loop gain and phase, I found that the dc gain, unity gain frequency and phase margin are different in different loading condition.
How can I deal with it? Could you give me some suggestions?
yes, dc gain, unity gain frequency and phase margin are different in different loading condition.
because the load res will changed the output pole,and the ESR will add a zero,if your regulator have a large output cap,you must simulation the condition of max output current
hi, szekit! u say worst case stability is at min output current and max output cap,
why the worst case stability is at these case? could u plz give a detailed commentate, thanks!