[SOLVED] Problem of making a JK flip flop

[gone]

hi all,

i am trying to use a SR latch and two 3-input NAND gates to implement a JK flip-flop

i tested SR latch and the nand gate separately, they all function well

but when i combine them into a JK flip flop, it cant work

the simulation graph is attached (j and k are equal to vdd) , i dont have any idea what causes the problem

thanks

 

[erikl]

Seems it isn't edge- but state-sensitive. Could you show your corresponding schematic?

 

[gone]

i just built the very simple JK- flip flop, so i have no idea of the cause of the problem ....

 

[erikl]

I think it's a setup or hold pb. You additionally should latch the outputs. See this one: JK Flip Flop