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Simulation of a self-biased reference


Junior Member level 1
Apr 4, 2012
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I am simulating in LTSpice the self-biased reference shown below without any startup circuit.
This is fig. 20.15 of J. Baker 4th ed.
I used L=2u for all transistors with W/L as shown on the figure.
Models are N_1u and P_1u from


I was wondering wether a start-up circuit is really necessary here if the P current mirror
sets a current ratio different from 1. So I first simulated the circuit as it is and without any start-up
hoping it would settle to a zero-current state with Vg,n=0 and Vg,p=Vdd.

However, I can't manage to get the circuit to settle this 0-current OP by simulation
-- A transient simulation with Vdd going from 0 to 10 gets to the 20uA OP (which is the other equilibrium for this circuit)
-- a DC simulation on the same range leads to the same results, even with a .IC or .NODESET statement
-- A .OP simulaltion with a .NODESET statement for the gate voltages leads again to the same results.

I was wondering if anybody could help
Thanks in advance
There are two or three stable states of this simple PTAT.
Off, current-locked and in the case of its bipolar cousin,
possibly a higher current caused by the reference devices
N and P saturating and messing up the mirror gain in a
"runaway until you hit the wall" sort of way.

Of course if you build it without a startup you will find a way
for it to not-start. Probably at slow corner low temp where
there's no strong junction or subthreshold leakage to boot on.
Bipolars with their base current demand set a higher bar
for startup.
Your zero current state depends on a bunch of things to happen together.

Vds mismatch in the PMOS Mirrors will cause the currents to be different by default, causing positive feedback to be stronger.
Vth mismatch in the NMOS Mirrors due to different Vsb will also cause the currents to be different, causing negative feedback to be stronger.

If, for some reason, you want to see your reference go into the 0uA point, you would want to run the simulation with
  1. Minimum Temperature, to reduce leakage effects which could kickstart your circuit.
  2. Supply at such a point that the Vds of M3 is much less than Vds of M4. i.e the mirror ratio in M3/M4 is <1.
  3. Give a S-L-O-W ramp to the VDD. This will avoid any capacitive coupling causing the your circuit to kickstart.
Wow. Thank you guys so much for your answers!!
This is the best forum ever :)

Reducing temp and/or making Vsb=0 in M2 didn't help.
But removing channel length modulation did :)

The models on are level 3 and I didn't know how to remove CLM
in a level 3 model, so I made them level 1 and added LAMBDA=0.
There is no more current mismatch between the 2 branches and I finally managed to get the 0-current state
or the 20u state depending on my .nodeset statement.

If you don't mind, I am gonna take advantage of the opportunity :)
The way I understand the circuit, Id1 and Id2 follow 2 different curves with respect to Vg,n.
This 2 curves only meet a 2 points with Id1=Id2=0 or Id1=Id2=20u
This behavior is confirmed by the following simulation


When using a P current mirror to enforce Id1=Id2, I understand a startup circuit is necessary to prevent the circuit to settle to the 0-current equilibrium.

So my question is: if, instead of a P current mirror with a 1:1 ratio, we choose something different, like 1:1.5,
is a startup circuit still necessary? Is this not exactly why I couldn't get the 0-state in the simulation myself?
I confess it is not very clear why a startup circuit is absolutely necessary here.
Baker himself use a transistor W/L=10/100 in the startup which I guess it would be nice to avoid.

Anyway, thanks again very much to both of you for your answers

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Basically in the 0 current situation, you want the positive feedback to be strong. For that you are keeping the current mirror ratio for both PMOS and NMOS >1.

While this should always work, there is the situation of true 0 current. Where still 0 x Large Mirror Ratio = 0. So in theory you would be stuck in 0 current mode.
Unless you have some leakage which can get multiplied and kickstart the circuit.

Speaking of leakage though, where does it come from and where flow through? Does leakge current from the PMOS M3 flow as Ids of the NMOS M1 and hence getting multiplied in M2 or does it flow as diode leakage Idb and hence the Ids remains 0 and the current is not mirrored.

It is somewhat luck I suppose now since leakage would not even be modelled accurately.

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