Powering a CMOS IC from a logic signal?

[Jester]

Circuit explanation:


Multi-tap SPI BUS with chip selects for each tap. The external SPI devices fail from time to time and one failure can bring down the entire bus (by forcing any one of the three signals to an in-appropriate state). Goal is to allow continued partial communication when one node fails.

If I use the following triple buffer: https://www.fairchildsemi.com/datasheets/NC/NC7NZ34.pdf for the SPI lines, and if I control the power to each buffer chip individually the bad node can be isolated.

Each buffer only drives one logic input at a time (all others are high-Z because they are powered down)

ARM processor that can sink or source 25mA on I/O pins. Is there any reason why I can't simple power the buffers from the 25mA capable I/O pins? (I guess they might not like charging the 100nF decoupling cap for the buffer).

Thoughts please

 

[KlausST]

Hi,

maybe it´s possible. But I don´t like it. The datasheet should tell if the levles of supply and logic are within the specified range.

****
SPI:
I assume the ARM is the master.

* Then there are thre lines out: MOSI, SCK and CS (or SS). No device at the bus must draw signifcant current form these lines. At the devices all thes signals are inputs. So I see no reason why a divece can make the bus to "hang" caused by these three lines.

* then there is one input: MISO. This is the critical line, because all devices may drive this line. But it should be very clear that only one should drive the line. Wich one is selected by the CS line.
You should ensure that only one device hase the cs line active. Usually the CS line is active low.
A 74HC138 can be used as selector for the CS lines.

A device with CS = high (inactive) must tri-state (high Z) it´s MISO output.
A device with CS = low (active) must drive it´s MISO output.

***
I used SPI many times, never had any problems with it.

***
If you need detailed help, you should provide more detailed informations. Schematic, code, ...


Klaus

 

[Jester]

Hi,

maybe it´s possible. But I don´t like it. The datasheet should tell if the levles of supply and logic are within the specified range.

****
SPI:
I assume the ARM is the master.

* Then there are thre lines out: MOSI, SCK and CS (or SS). No device at the bus must draw signifcant current form these lines. At the devices all thes signals are inputs. So I see no reason why a divece can make the bus to "hang" caused by these three lines.

* then there is one input: MISO. This is the critical line, because all devices may drive this line. But it should be very clear that only one should drive the line. Wich one is selected by the CS line.
You should ensure that only one device hase the cs line active. Usually the CS line is active low.
A 74HC138 can be used as selector for the CS lines.

A device with CS = high (inactive) must tri-state (high Z) it´s MISO output.
A device with CS = low (active) must drive it´s MISO output.

***
I used SPI many times, never had any problems with it.

***
If you need detailed help, you should provide more detailed informations. Schematic, code, ...


Klaus

Klaus,

The CS is functioning just fine, the failure mode is caused by the short cable (2' ) that connects each slave to the master, after some time the cables go bad and then anyone of the signals can go open or become shorted to ground or Vcc. Open is not so bad as it just makes that channel inoperable, the more common scenario is that the CLK or MISO line gets pulled to ground making all channels inoperable.

 

[BradtheRad]

failure mode is caused by the short cable (2' )

* Perhaps a series capacitor somewhere? It blocks DC current. However this would result in AC waveforms on your signal lines, requiring waveform conditioning at the receptors.

* The method of one-wire communication sometimes comes up here. Don't know how it works. It might be a solution for your setup.

* Lightwave communication? LED's are feasible over a short distance. Or else fiber optics.

 

[KlausST]

Hi,

The cable is the problem....
Then I recommend to use a high quality cable...

If you want to communicate with an SPI device, then you should remove the cable problems.
If the SPI device is not necessary, then don't connect it at all.

Klaus

 

[Jester]

This system has been in place for quite some time, so the cable and pin out need to remain the same for compatibility with existing end modules. The actual failure rate is low, however there are a lot of units out there, so over time the cables go wonky after being manipulated too many times.

I'm looking for a compatible solution that will prevent the entire bus from going down when we have one shorted cable. The head unit software can detect a bad end unit when it's simply open or not talking for whatever reason.

 

[BradtheRad]

This doesn't prevent the problem but...
Consider installing an led or two, to give you a visible alert whether a bus wire is at the wrong state. Perhaps add a timing circuit to tell you it has been stuck in the same state too long. You might need several such circuits, depending on how many bus wires you want to monitor.

 

[mrinalmani]

Instead of using a buffer with all the peripherals, use one single buffer in series with the four SPI BUS lines. This will strengthen the driving capacity of the serial lines. Now you may use a 4.7K to 20K resistor in series with all the tap lines connecting individual peripherals. Even if a peripheral fails, it will short the BUS line through the series resistors and not a direct short.
Sine the BUS line is being driven by the buffer, the buffer can easily maintain the signal levels while simultaneously providing current to the short resistor. It can easily provide up to 20mA current.
Worst case, even if all four lines of a device short out to ground. The maximum current drawn in case of 10K series resistor will only be 5/2.5K = 2mA which can easily be handled by the buffer. Even if 10 devices fail, the buffer will maintain the BUS levels