extracting carrier signal

[gary36]

I have a signal with relation A sinw1t cos(phi-w2t). w1 = 50Hz and w2=1khz. I need to extract carrier from the product. I tried using Band pass filter with cut off 750 hz and 1500 hz. I am unable to get the second term properly. Tried different combinations, but with little success. Help required to get the right method of extraction.

 

[kaz1]

I have a signal with relation A sinw1t cos(phi-w2t). w1 = 50Hz and w2=1khz. I need to extract carrier from the product. I tried using Band pass filter with cut off 750 hz and 1500 hz. I am unable to get the second term properly. Tried different combinations, but with little success. Help required to get the right method of extraction.

If you mean extract w1 and w2 through filtering then apply a filter for w1 and another for w2.
if you want extract w1 to w2 range the apply bandpass from < 50Hz to > 1kHz

 

[gary36]

I tried extracting signal with w2 as mentioned in #1, but I do not get response waveforms of the second signal.

 

[kaz1]

I tried extracting signal with w2 as mentioned in #1, but I do not get response waveforms of the second signal.

Do you have your signal file or how you generated it:
I did this to generate it in Octave:

A = 1;
phi = 0;
w1 = 50;
w2 = 1000;
t = 0:.1:1000;
x = A*(sin(w1.*t).* cos(phi-w2.*t));

 

[dick_freebird]

When you say "extract", that could mean different things.

If you want to regenerate the carrier at a stable amplitude and
frequency you probably want a PLL that can "ride out" the
envelope passing through zero twice a cycle.

If you believe that carrier is stable and don't want such elaborateness,
and you know where the carrier should be, then perhaps a high Q 1kHz
tank fed from a high pass filter would ring up the way you want and
smooth over all those zero crossings.

It's on you to define the "values" at the higher levels, which will
narrow the field of viable choices.

 

[FvM]

f1 is 8.8 Hz, f2 is 157 Hz, there's no output left with 750 to 1500 Hz bandpass.

 

[gary36]

From #5.
1. What is the logic behind using high pass filter and tank circuit?
2.Could you please elaborate on design of high Q tank circuit. Can you suggest configuration of active tank circuit and how to choose the values?
And what should be Fc for high pass filter. It is not clear? Can both be combined in single implementation?

 

[FvM]

Except already mentioned confusing of omega and f, the modulated signal is DSB with suppressed carrier, respectively you get two frequencies f2+f1 and f2-f1 in output. Can't extract f2 with a simple filter.

 

[gary36]

You mean use a tank circuit to extract the carrier and eliminate the rest. Should it be bandpass or notch?

 

[gary36]

BTW, I tried parallel RLC circuit with resonant frequency as 1KHz and I am able to get carrier signal output with smooth transition at zero crossings. Thank you for the support

 

[BradtheRad]

Can both be combined in single implementation?

Join a capacitor and resistor in series. Tap across one to obtain low frequencies. Tap across the other to obtain highs.

The filter effect is partial though it illustrates the concept. If you want better separation you can install op amp filters, etc.

 

[D.A.(Tony)Stewart]

The Q must be result in a BW much less than the AM f = 50 Hz

if Q=1k/50 =20 thus Q=50 would be ideal and not too sensitive.

 

[FvM]

Several contributions seem still to ignore that the modulated signal has spectral lines f2+f1 and f2-f1, but neither f2 nor f1.

 

[gary36]

I tried simulating RLC parallel resonant circuit with several combinations and as suggested in #13, the output does not contain f2 or f1 but f2+f1 and f2-f1. It looks like this circuit may not be perfectly suitable for extracting the carrier. Besides the group delay introduced by the tank circuit is also substantial. Do we have any alternate methods?

 

[FvM]

More exactly, it's not possible to extract the carrier (continuous f2 signal) with a linear circuit. The specific problem is that modulated signal phase switches with modulation signal polarity. Possible solution is e.g. a Costas loop PLL. I guess a bit more complex than you thought.

Costas loop - Wikipedia

en.m.wikipedia.org

 

[FvM]

Here's a demonstration of Costas loop detector in LTspice

 

[gary36]

I tried to manipulate the tank circuit again, this time I fixed the resonant frequency to be 50Hz. Now I converted the resultant output to square wave and I could notice 1KHz signal. Only limitations is that the output signal is not smooth at zero crossings resulting in broader pulse width in this region. Comparing the output with a reference 1 KHz gave me the necessary phase difference correspondence of the value of Phi. Looks like coming close to solution, but not quite there.

 

[FvM]

Your latest post raises doubts if you clearly specified what you want to achieve. I understand carrier as continuous, unmodulated f2 signal.

 

[gary36]

Yes truly I wanted f2, but without too much of complexity. Objective is to extract the phase difference and compare with the reference signal to estimate the change in phase. Any further advice?

 

[D.A.(Tony)Stewart]

Please correct your formula and help us understand your goal and what hardware/software you are working with. I think you meant ω1 = 2πf1 rather than w1 = 50 Hz.

I see in the spring you were doing something similar and a reference was given to you by @danadakk. https://www.edaboard.com/threads/phase-sensitive-detection.406374/post-1751078

https://tinyurl.com/yn8xu5ts I made this BPF with a very high GBW (100MHz) to achieve a Q of 50 at 1KHz.

When the deviation Δfc of the carrier centre, is much broader than a BPF there will be some fraction of a cycle that can stimulate ringing in the BPF. But there exist many deviations of Δfc where the power is null because the average energy of phase of the carrier fc cancels out sweeping up then down with a wide-band FM modulator.

e.g. fc= 1kHz, f1= 50 Hz These nulls exist near Δfc = n*fc/4 ± fm for n = 1, 2, 3 ...

The amount of jitter in a limited clock using a simple narrow BPF will thus depend on the deviation ratio m=Δfc/fm.

So it is possible for some random deviation ratio to recover some variable jitter clock, but this is not how one designs a demodulator or clock recovery circuit.

Many methods were used to recover the clock in the old hard disk days of MFM with carrier pulses of 1T, 1.5T, and 2T for a 10 MHz cycle = 1T. But we need more input on your intentions. Generally, a PLL is the best solution with a controlled loop rate.