Jester
Full Member level 6
Circuit explanation:
Multi-tap SPI BUS with chip selects for each tap. The external SPI devices fail from time to time and one failure can bring down the entire bus (by forcing any one of the three signals to an in-appropriate state). Goal is to allow continued partial communication when one node fails.
If I use the following triple buffer: https://www.fairchildsemi.com/datasheets/NC/NC7NZ34.pdf for the SPI lines, and if I control the power to each buffer chip individually the bad node can be isolated.
Each buffer only drives one logic input at a time (all others are high-Z because they are powered down)
ARM processor that can sink or source 25mA on I/O pins. Is there any reason why I can't simple power the buffers from the 25mA capable I/O pins? (I guess they might not like charging the 100nF decoupling cap for the buffer).
Thoughts please
Multi-tap SPI BUS with chip selects for each tap. The external SPI devices fail from time to time and one failure can bring down the entire bus (by forcing any one of the three signals to an in-appropriate state). Goal is to allow continued partial communication when one node fails.
If I use the following triple buffer: https://www.fairchildsemi.com/datasheets/NC/NC7NZ34.pdf for the SPI lines, and if I control the power to each buffer chip individually the bad node can be isolated.
Each buffer only drives one logic input at a time (all others are high-Z because they are powered down)
ARM processor that can sink or source 25mA on I/O pins. Is there any reason why I can't simple power the buffers from the 25mA capable I/O pins? (I guess they might not like charging the 100nF decoupling cap for the buffer).
Thoughts please