hi.can anybody tell me how to do gatelevel simulation.i mean i want to verify my netlist generated by synthesis tool.wen i exported my netlist to simulator ,it is showing some components r unresolved.do i need to supply any synth lib to simulator.i am using cadence RTL compiler for synth,NCsim for simulation
do u mean to supply which lib files.my synth lib files r not in the .v format.do i need to compile simulator librery file or synth lib file.plz elaborate
Neslist has some tech library files (depends on fab technology 90 nm 130 nm....) and all memory models so u have to compile all memory models used in the netlist and all tech library ( TSMC or others) before annotating with sdf.
can u elaborate.synth lib files r not in the .v format.how to get
Added after 2 minutes:
my netlist has a ADDFX1 component.that is my standard cell present in the synth lib,which is typical.lib.how to resolve addfx1 component.where can i get verilog format of the addfx1 cell
If your library is complete you should have datasheets for each cell, the db files, the verilog description, scan description for ATPG... the lot... lef/def files....
Ask your vendor to supply these to you... although I am sure they are included in your library delivery
1. I would go by what hash_delay has said. It would solve your problem
2. You dont need an sdf file. YOu can do sims without it.
sdf is anyway only relevant when you do sims after layout.
kr,
Avi http://www.vlsiip.com
i cant find any lib with verilg extension in my lib files.i am using cadence university license .i think they dont supply full libraries for student programs
even though u are using cadence university license, they will be supplying libraries. by the way how you synthesized your design either generic or mapped
open ur cadence synthesis setup file and see the path of your library file you use to synthesize ur design.
copy this path into your NC sim tool and go to the location, it opens into your library files directory , here you look for verilog folder, open it and you can see your lib file, compile it and next proceed normally with ur simulation