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post synthesys simulation

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Member level 4
Feb 28, 2007
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hi.can anybody tell me how to do gatelevel simulation.i mean i want to verify my netlist generated by synthesis tool.wen i exported my netlist to simulator ,it is showing some components r i need to supply any synth lib to simulator.i am using cadence RTL compiler for synth,NCsim for simulation

You will need to supply the standard cell libaries to nc-sim. to suplly the libs to simulator.wat is the procedure

u have a .v or .vhd library file.
just check in ur installation directory.
compile it with ur .v or .vhd netlist file.

Just compile your all library files with ncvhdl/ncvlog and then run with netlist. Since in your netlist library files are used for synthesis.

do u mean to supply which lib synth lib files r not in the .v i need to compile simulator librery file or synth lib file.plz elaborate

Your libraries should have a complete verilog description of each of your gates.
These should be compiled with your simulator.

Also, do not forget the SDF. In many cases a netlist without SDF will not work, especially if you have complex clock generation methods.

So, do not forget to annotate the SDF on your netlist.

u should provide a type of lib which can be recognized by simulator, the annotate the sdf file

Neslist has some tech library files (depends on fab technology 90 nm 130 nm....) and all memory models so u have to compile all memory models used in the netlist and all tech library ( TSMC or others) before annotating with sdf.

can u elaborate.synth lib files r not in the .v to get

Added after 2 minutes:

my netlist has a ADDFX1 component.that is my standard cell present in the synth lib,which is to resolve addfx1 component.where can i get verilog format of the addfx1 cell

If your library is complete you should have datasheets for each cell, the db files, the verilog description, scan description for ATPG... the lot... lef/def files....

Ask your vendor to supply these to you... although I am sure they are included in your library delivery

wat is the command for sdf file generation in RTL compiler

NC-Verilog Simulation tool for adding library for netlist sims:

You need to add

-y /<directory path of the library here>/unisims +libext+.v

Here unisims would be library name
You can supply this via command line or at the start of the list of files.

1. I would go by what hash_delay has said. It would solve your problem
2. You dont need an sdf file. YOu can do sims without it.
sdf is anyway only relevant when you do sims after layout.

i cant find any lib with verilg extension in my lib files.i am using cadence university license .i think they dont supply full libraries for student programs

Hi nikhil,

even though u are using cadence university license, they will be supplying libraries. by the way how you synthesized your design either generic or mapped

when u added the sdf in your simulation,the delay of design can be showed

if u just compiled the .v lib in your sim tool,that should be ok,just show you function verification

it will be realized with start simulation menu in modelsim.

see nikhil it goes this way

open ur cadence synthesis setup file and see the path of your library file you use to synthesize ur design.

copy this path into your NC sim tool and go to the location, it opens into your library files directory , here you look for verilog folder, open it and you can see your lib file, compile it and next proceed normally with ur simulation

reply me for any queries

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