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Member level 4
Aug 19, 2007
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1.How do u check whether our clock is reaching to all the paths ?
2.What is shrink factor ?
3. Is it possible to have zero skew in our design??
4.what is the difference between power analysis and rail analysis ?
5. Is it possible to have power bounce in SOC encounter??
6. Why u do power analysis?
7. How do u calculate the width of the stripes??
8.What was ur die size??
9. Instead of giving the power rings around the core area can i put it on the core area ? If yes then how???


Hey santu these are the questions asked for me dear so ur asking hehehhe
ok anyway
i know some of the answers
6 ) we do power analysis to find out the IR drop of the net so if we know the IR drop then we can minimise it right by taking some of the techniques....
8) we can calculate the die size as u know that the (core area + core margin area + i/o pad area )will give u the total die size ok
and generally die size will be there in ur .DEF file the tool will automatically calculates and gives u

Added after 3 minutes:

The last answer is u can put the core rings on the core area by giving the negative offset in power planning option but wt happens is there will be a signal integrity problems so thats y we put the core rings around the core area... hope this is clear to u

Dear mujju,

OF course man , its yours only no doubt.

but it was hidden i helped to make it out


it seems to be a good "group" discussion.....well ..nice ....:D

Hi friends
Ans1) Actually we can't check practically that the clock is reaching to all path at the same time. But we can take care of this during clock routing by calculating path depalys and arrenging blocks accordingly. Clocking strategies like H-tree can be used. Thus clock routing is always treated separate
issues in camparison to normal routing.
3) yes
6) Power analysis is done to get the total power, leackage power, static power dissipation and to check wether they are in within limitation or not.

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