I find myself curious about this circuit. I think I am missing something because it appears to me that Q1 and Q3 counteract each other, with Q6 countering the current influence of Q3, If Q3,Q4,Q5,Q6 equal in size, then they all cancel the push/pulling of current from each other, meaning just Q1 and Q2 determine Vo. I do not see the point of this. I have seen positive feedbacks implemented in latches but not in this manner, but normally in the manner that if a Q1 gate voltages goes up it starts to pull vo down, as vo starts to go down a pfet gate connected to it would start conducting more current in the Q2 leg. basically being a double impact circuit. This is what Q5 and Q6 are doing, but the Q3 and Q4 seem to counter that. Refreshing myself in a book this appears closer to a track and latch comparator, with the latch reset being tied to the output. So I guess I am confused about the need for Q3 and Q4. Also I could see use if Q5/Q3 >1 then you are adding hysteresis. But in the paper this is not the case..
So I am still a little confused about this.
-Pb
As a rather trivial fact, any change to the gain with otherwise constant parameters (pole locations) affects the phase margin, so does the shown cross-coupled current-mirror load.
you need to overlap the phase plots, its obvious the partial pos feedback has higher dc gain, and lower bw. I expect the phase plot and poles have shifted slightly just hard to see without overlap. you are adding an additional Cgs and Cdb load on the output, this will move poles and change bw.
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besides the parasitic caps being added, you are significantly changing the output impedance. in the original your gain was gm * 1/(gds1+gds3). the pos fb version has ro= 1/(gds1+gds3+gds5), so you have reduced your gain from q1 but added a parallel gain from q2 via q6 (2 stage cs amp). and as you know the pm is lesser on a higher order amp. even when used in this case as a pos feedback addition to a comparator.
-Pb
you need to overlap the phase plots, its obvious the partial pos feedback has higher dc gain, and lower bw. I expect the phase plot and poles have shifted slightly just hard to see without overlap. you are adding an additional Cgs and Cdb load on the output, this will move poles and change bw.
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besides the parasitic caps being added, you are significantly changing the output impedance. in the original your gain was gm * 1/(gds1+gds3). the pos fb version has ro= 1/(gds1+gds3+gds5), so you have reduced your gain from q1 but added a parallel gain from q2 via q6 (2 stage cs amp). and as you know the pm is lesser on a higher order amp. even when used in this case as a pos feedback addition to a comparator.
-Pb
Hi Junus,
finally, I don`t know what your problem is. Please, explain in detail.
Let me summarize:
1.) You have a circuit (without internal pos. feedback) with certain gain and phase characteristic. Gain is approx. 70 dB.
2.) Resulting from internal pos. feedback the gain is somewhat increased and the phase is enhanced. This gives an improved phase margin.
3.) These results are confirmed via simulation.
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So everything works and behaves as expected. What is the problem?
Nr. 2, the phase margin is in reverse, it is decreased , however this is right. the phase margin must degrade when a positivist feedback is applied, but my problem I want to explain scientifically why.
No - the margin is increased ! Have a look on the phase response, which is ABOVE the curve without feedback!
But I forgot to answer point 2) of your initial inquiry:
It is not a requirement that the 2nd pole is beyond the GBW (gain cross-over).
It depends on the margin requirements under worst case conditions (unity feedback).
Very often there is a trade-offbetween margin and bandwidth. Remember that there are uncompensated opamps with bad margins (for low gains) but higher bandwidth.
Dear LvW, 'The phase margin without p.F is 68, with the P.F is 49, so it means it decreased
please leave this figure it is not that clear, refer to the first one of my post with the separated results , the curve with the DC gain of 81 is the circuit with the positive feedback
the second graph with the DC gain of 74 is without the positive feedback
I dont know what you mean to say by my self, I am using mentor graphic tools which are industry dependent tools, and the phase margin is obvous from the AC test, what the problem with that ????
any way I am sorry if I got you confused with the overlaped plot,
And what´s wrong with the second (overlapped) graph? Of course, I have used it as a basis for my answer.
I think, without knowing whether resp. why it should/could be wrong you even cannot trust the first diagrams.
With the wording "...by yourself" I refer simply to the definition of the PM, which is based on the phase at the gain cross-over frequency, which always can be seen in the BODE diagram
I do not blindly trust any calculated numbers on the screen without knowing how the are generated.
I dont know what exactly is the wrong ?? the phase margin as you said is calculated at the GBW = 0. I only attached the overlaped picture prestonne asked me about it.
However , is there any mistake in the results ??
I only can see that the first diagrams do not match with your last diagram because different margins can be identified.
(Example without internal "feedback": gain cross-over phase=110 deg in the 1st and 125 deg in the last diagram.)
I don`t know how this diagram was created.
More than that - I don`t know what "kind of gain" the diagrams show.
* OTA output voltage with or without external load? Output resistance variation with/without internal feedback?
* OTA output current vs. input voltage?
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