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# phase margin issue with a positive feedback in current mirror OTA

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#### Junus2012

##### Advanced Member level 5
Hello Analog guys

I designed a current mirror OTA with a partial positive feedback, the circuit is like the one I attached from Gregorian book, Figure Nr. 3.41.

After I finished the design , I have simulated the circuit with and without the positive feedback as shown in the first and second image respectively.

Here I have a couple of questions,

1. I believe that the positive feedback degrade the Phase margin as you can see fro the both images , but I need an explanation on this circuit how is degrading. I am thinking that this positive feedback because it reduces the effective load transconductance, then the second pole becomes at lower frequency toward the dominant pole. is it right assumption ????

2. in Holberg book he said for stable op-amp, the second pole should be beyond the GBW, but I see that in both cases the second pole is before the GBW, isn't it, please could you tell me where it is exactly in both cases ???

3. This positive feedback supposed not not to alter the GBW, but from the images it did effect, whay ??

Thank you very nuch
I need your help in this post very badly

#### Attachments

• ota3.pdf
69.6 KB · Views: 117
• ota2.JPG
198 KB · Views: 109
• ota1.JPG
191.2 KB · Views: 95

I find myself curious about this circuit. I think I am missing something because it appears to me that Q1 and Q3 counteract each other, with Q6 countering the current influence of Q3, If Q3,Q4,Q5,Q6 equal in size, then they all cancel the push/pulling of current from each other, meaning just Q1 and Q2 determine Vo. I do not see the point of this. I have seen positive feedbacks implemented in latches but not in this manner, but normally in the manner that if a Q1 gate voltages goes up it starts to pull vo down, as vo starts to go down a pfet gate connected to it would start conducting more current in the Q2 leg. basically being a double impact circuit. This is what Q5 and Q6 are doing, but the Q3 and Q4 seem to counter that. Refreshing myself in a book this appears closer to a track and latch comparator, with the latch reset being tied to the output. So I guess I am confused about the need for Q3 and Q4. Also I could see use if Q5/Q3 >1 then you are adding hysteresis. But in the paper this is not the case..
-Pb

As a rather trivial fact, any change to the gain with otherwise constant parameters (pole locations) affects the phase margin, so does the shown cross-coupled current-mirror load.

yes the circuit itself can be used as a latch or hysteresis comparator, this is another part of the book where you can find your interest about this circuit

I find myself curious about this circuit. I think I am missing something because it appears to me that Q1 and Q3 counteract each other, with Q6 countering the current influence of Q3, If Q3,Q4,Q5,Q6 equal in size, then they all cancel the push/pulling of current from each other, meaning just Q1 and Q2 determine Vo. I do not see the point of this. I have seen positive feedbacks implemented in latches but not in this manner, but normally in the manner that if a Q1 gate voltages goes up it starts to pull vo down, as vo starts to go down a pfet gate connected to it would start conducting more current in the Q2 leg. basically being a double impact circuit. This is what Q5 and Q6 are doing, but the Q3 and Q4 seem to counter that. Refreshing myself in a book this appears closer to a track and latch comparator, with the latch reset being tied to the output. So I guess I am confused about the need for Q3 and Q4. Also I could see use if Q5/Q3 >1 then you are adding hysteresis. But in the paper this is not the case..
-Pb

#### Attachments

• Introduction to CMOS OP AMPS and Comparators (Roubik Gregorian).pdf
482.7 KB · Views: 74

back to my circuit, still the reason is not known, specially i see that the both poles in both circuits are equal unless if i am wrong

- - - Updated - - -

Dear FvM, I just see your comment now. I believe that you can help me to understand the reason.

I did not get your answer, please you will do a favour of me as usual if you kindly can answer my question according to the numbers (1, 2, 3)

Thank you in advance
Regards

As a rather trivial fact, any change to the gain with otherwise constant parameters (pole locations) affects the phase margin, so does the shown cross-coupled current-mirror load.

you need to overlap the phase plots, its obvious the partial pos feedback has higher dc gain, and lower bw. I expect the phase plot and poles have shifted slightly just hard to see without overlap. you are adding an additional Cgs and Cdb load on the output, this will move poles and change bw.

- - - Updated - - -

Error Fix: I made a wee little math mistake output impedance is 1/(gm3+ gds1 + gds3) ~ 1/gm3, this doesnt change with the addition of pos feedback.
so the gain change is really just the addition of the pos feedback. I still stand by my impacts of parasitics on the poles though.
-Pb

Last edited:
Junus2012

### Junus2012

Points: 2
Dear prestonee

i attached you the overlaped image
hope it is clear

you need to overlap the phase plots, its obvious the partial pos feedback has higher dc gain, and lower bw. I expect the phase plot and poles have shifted slightly just hard to see without overlap. you are adding an additional Cgs and Cdb load on the output, this will move poles and change bw.

- - - Updated - - -

besides the parasitic caps being added, you are significantly changing the output impedance. in the original your gain was gm * 1/(gds1+gds3). the pos fb version has ro= 1/(gds1+gds3+gds5), so you have reduced your gain from q1 but added a parallel gain from q2 via q6 (2 stage cs amp). and as you know the pm is lesser on a higher order amp. even when used in this case as a pos feedback addition to a comparator.

-Pb

- - - Updated - - -

Dear prestonee

i attached you the overlaped image
hope it is clear

you need to overlap the phase plots, its obvious the partial pos feedback has higher dc gain, and lower bw. I expect the phase plot and poles have shifted slightly just hard to see without overlap. you are adding an additional Cgs and Cdb load on the output, this will move poles and change bw.

- - - Updated - - -

besides the parasitic caps being added, you are significantly changing the output impedance. in the original your gain was gm * 1/(gds1+gds3). the pos fb version has ro= 1/(gds1+gds3+gds5), so you have reduced your gain from q1 but added a parallel gain from q2 via q6 (2 stage cs amp). and as you know the pm is lesser on a higher order amp. even when used in this case as a pos feedback addition to a comparator.

-Pb

- - - Updated - - -

by the way I am not mentioning the reduction in the op-amp open loop bandwith, this obviously decrease with higher gain. but i was asking about the GBW that must be constant while it is changing in my case when the p f.B is applied

I think you have the phases switched, the phase you state is without feedback is always worse phase margin then the other, so the gain associated with it should always has less phase margin. But with the overlap you can see that in fact both the dominant and non-dominant poles are pushed a little to the left degrading the phase margin. If your tag is correct, then this is just bizarre. because then you are stating that you added pos feedback, increasing both gain and phase margin.

-Pb

Hi Junus,

finally, I dont know what your problem is. Please, explain in detail.
Let me summarize:
1.) You have a circuit (without internal pos. feedback) with certain gain and phase characteristic. Gain is approx. 70 dB.
2.) Resulting from internal pos. feedback the gain is somewhat increased and the phase is enhanced. This gives an improved phase margin.
3.) These results are confirmed via simulation.
__________________
So everything works and behaves as expected. What is the problem?

- - - Updated - - -

Additional remark: I cannot confirm the indicated phase margins.
Instead, I read approx: 55 deg (without feedback) and 70 deg (with feedback).

Hello LvW

Nice to see you here

Nr. 1 is as you mentioned

Nr. 2, the phase margin is in reverse, it is decreased , however this is right. the phase margin must degrade when a positivist feedback is applied, but my problem I want to explain scientifically why.

I have given a reason of that but I am not sure if it is right or not, I will explain it you again, this positive feeback as you see from the pdf attachment, it enhance the gain by increasing the transconductance of the differential amplifier, by other words it decrease the load resistance (or increase its transconductance)of this kind of differential amplifier and hence the gain will increase(Av= gm1/gm2)

now

I have used this differential as an input stage of cascoded current mirror OTA as shown in this attachment. the output resistance is very high so the dominant pole is at lower frequency as you see from the results I posted before. while the resistance gain of the first stage is small, thus the second non dominant pole is at higher frequency keeping a large distance from the dominant pole and hence the circuit is self compensated circuit.

I am sorry to make it long, but you asked me about the details

I hope now it is possible to find the scientific reason about how this positive feedback is degrading the gain of the complete OTA, that is what I need

Thank you very much, I am looking forward for your kind reply

Note: the circuit i am simulating has a cascoded output rather

Hi Junus,

finally, I dont know what your problem is. Please, explain in detail.
Let me summarize:
1.) You have a circuit (without internal pos. feedback) with certain gain and phase characteristic. Gain is approx. 70 dB.
2.) Resulting from internal pos. feedback the gain is somewhat increased and the phase is enhanced. This gives an improved phase margin.
3.) These results are confirmed via simulation.
__________________
So everything works and behaves as expected. What is the problem?

Nr. 2, the phase margin is in reverse, it is decreased , however this is right. the phase margin must degrade when a positivist feedback is applied, but my problem I want to explain scientifically why.

No - the margin is increased ! Have a look on the phase response, which is ABOVE the curve without feedback!

But I forgot to answer point 2) of your initial inquiry:
It is not a requirement that the 2nd pole is beyond the GBW (gain cross-over).
It depends on the margin requirements under worst case conditions (unity feedback).
Very often there is a trade-offbetween margin and bandwidth. Remember that there are uncompensated opamps with bad margins (for low gains) but higher bandwidth.

Junus2012

### Junus2012

Points: 2
Dear LvW, 'The phase margin without p.F is 68, with the P.F is 49, so it means it decreased

I will discuss your answer regarding the poles after clearing this in order not to confuse you with my questions

No - the margin is increased ! Have a look on the phase response, which is ABOVE the curve without feedback!

But I forgot to answer point 2) of your initial inquiry:
It is not a requirement that the 2nd pole is beyond the GBW (gain cross-over).
It depends on the margin requirements under worst case conditions (unity feedback).
Very often there is a trade-offbetween margin and bandwidth. Remember that there are uncompensated opamps with bad margins (for low gains) but higher bandwidth.

Dear LvW, 'The phase margin without p.F is 68, with the P.F is 49, so it means it decreased

Do you blindly trust some figures on the screen? Do you know how they are generated?
Why dont you evaluate the phase response and the associated PM by yourself?
Is the blue curve in your last diagram above the yellow one? And what does this mean?

please leave this figure it is not that clear, refer to the first one of my post with the separated results , the curve with the DC gain of 81 is the circuit with the positive feedback

the second graph with the DC gain of 74 is without the positive feedback

I dont know what you mean to say by my self, I am using mentor graphic tools which are industry dependent tools, and the phase margin is obvous from the AC test, what the problem with that ????

any way I am sorry if I got you confused with the overlaped plot,

please leave this figure it is not that clear, refer to the first one of my post with the separated results , the curve with the DC gain of 81 is the circuit with the positive feedback

the second graph with the DC gain of 74 is without the positive feedback

I dont know what you mean to say by my self, I am using mentor graphic tools which are industry dependent tools, and the phase margin is obvous from the AC test, what the problem with that ????

any way I am sorry if I got you confused with the overlaped plot,

And what´s wrong with the second (overlapped) graph? Of course, I have used it as a basis for my answer.
I think, without knowing whether resp. why it should/could be wrong you even cannot trust the first diagrams.
With the wording "...by yourself" I refer simply to the definition of the PM, which is based on the phase at the gain cross-over frequency, which always can be seen in the BODE diagram
I do not blindly trust any calculated numbers on the screen without knowing how the are generated.

The phase margin is reduced by the added loading of parasitics on the output nodes from the additional drains and gates(affects both p1 and p2). thats the reason for the degraded pm.
To verify this, you could use a cccs to buffer the outputs from the additional drains, and vcvs to buffer the additional gates. This will allow you to have your pos feed back gain boost without impacting your parasitics on the drains of Q1 and Q2.
you can say the 1st pole is 1/R*Cout and this should help you understand how its impacted, 2nd Pole is 1/R*cout*Cin, these C's contain the miller effect of cgd, which is impacted by gm. so you can easily see that any change on Cout impacts both the 1st and 2nd pole.
-Pb

Last edited:
Junus2012

### Junus2012

Points: 2
Dear LvW

I also believe with that, of course the phase margin is very basic thing and I know how to find it manually, but believe me I dont know what exactly is the wrong ?? the phase margin as you said is calculated at the GBW = 0. I only attached the overlaped picture prestonne asked me about it.

However , is there any mistake in the results ??

hope now this cleared

still I am looking for your explanation about the mechanism of the phase degradation in my circuit

Thank you alot

And what´s wrong with the second (overlapped) graph? Of course, I have used it as a basis for my answer.
I think, without knowing whether resp. why it should/could be wrong you even cannot trust the first diagrams.
With the wording "...by yourself" I refer simply to the definition of the PM, which is based on the phase at the gain cross-over frequency, which always can be seen in the BODE diagram
I do not blindly trust any calculated numbers on the screen without knowing how the are generated.

I dont know what exactly is the wrong ?? the phase margin as you said is calculated at the GBW = 0. I only attached the overlaped picture prestonne asked me about it.
However , is there any mistake in the results ??

I only can see that the first diagrams do not match with your last diagram because different margins can be identified.
(Example without internal "feedback": gain cross-over phase=110 deg in the 1st and 125 deg in the last diagram.)
I dont know how this diagram was created.
More than that - I dont know what "kind of gain" the diagrams show.
* OTA output voltage with or without external load? Output resistance variation with/without internal feedback?
* OTA output current vs. input voltage?

Dear LvW

the test is open loop test
the simulated gain is the voltage gain

conditiion: pure capacitve load of 50 PF

please only consider the graphs from my first post, the phase margin is for sure changing because of the p.f

thank you for your patience

I only can see that the first diagrams do not match with your last diagram because different margins can be identified.
(Example without internal "feedback": gain cross-over phase=110 deg in the 1st and 125 deg in the last diagram.)
I dont know how this diagram was created.
More than that - I dont know what "kind of gain" the diagrams show.
* OTA output voltage with or without external load? Output resistance variation with/without internal feedback?
* OTA output current vs. input voltage?

Junus,

up to now you didnt tell us about the load capacitor.

Knowing this, I have the following comments:
* The additional circuitry (you call it "pos. feedback") enhances the transconductance and, thus, the overall gain. This is the desired and expected effect.
* At the same time the output resistance certainly will be effected - but I don`t know in which way. However, this modified output resistance - together with the capacitive load - will change the phase response of the whole circuit. Thus, no surprise.
* More than that, I think this additional "pos. feedback" cannot be compared with the "normal" pos. feedback (and it´s consequences) as known, for example, from opamps in the voltage feedback mode.
* That means: It is clear that the gain as well as the phase response is effected by the additional circuitry - however, I am not able to give further detailed explanations without time consuming additional investigations.

I am afraid, that´s all one can say - unless somebody has gained already some experience with this circuit.

Junus2012

Points: 2