HI jay_ec_engg,
Be carefule if you use XPLD's ram resource. It will make the P&R difficulty. And do not try to lock the pin by yourself, let the software to assign the pin itself.
And use the version later than 4.1. Try to use the 3rd part EDA software to fit the HDL, and then use LEVER to compile the edf file.
Hi Jay_ec_engg,
If you haven't use XPLD's memory resource, you do not need to care assigning pins.
Because the ram resource wasting too many router resource.
Do you know about SRAM configuration option with XPLD ?
How exactly can we implement it ???
RAM which u are talking about is this SRAM for configuration or RAM used for our application ???
Hey Jay now you can try with LAttice XP device as its teh best noon Volatile FPGA Infinite times reconfigurable.. try that out .. if you need an hekp lemme know
Hi Jay,
XP and XO are the new products of Lattice. These two products use the same XP technology just like XPLD. But they are much cheaper than XPLD. They are all LUT base device. XP is focus on low cost FPGA, XO is focus on large CPLD.
XPLD is just a name that Lattice has used to distinguish between this device family and a standard CPLD.
This device has FPGA I/O options, Memory and PLL's, and it also configures through a parallel uP bus besides the standard JTAG/B-Scan.