Lattice Diamond IP Pin Constraints

[stark43]

Hello, I will use "CSI-2/DSI D-PHY Transmitter Submodule IP" for Crosslink FPGA in Lattice Diamond. I want to know the pin setting of this IP, but I couldn't find which pins the IP uses and IP pin constraints. He gave an example as follows, but I couldn't see the source of it and I wonder how it was done.

LOCATE COMP "clarity_tx2_inst/csi2_raw10_output_inst/u_dphy_tx/pll_lock_o_I_0/clk_p_o_I_0" SITE "MIPIDPHY0" ;

I also want to see what pins the IP is using. For example, the E7 pin is used for clk. I will be grateful if you could help me.

--- Updated Sep 27, 2022 ---

IP doc : https://www.latticesemi.com/view_document?document_id=52137

 

[FvM]

I don't think that the IP has specific constraints, but it occupies one MIPI-D PHY. You should review the FPGA hardware documents for its requirements.

 

[stark43]

I don't think that the IP has specific constraints, but it occupies one MIPI-D PHY. You should review the FPGA hardware documents for its requirements.

I looked through the documentation but couldn't find it, unfortunately I also have a time problem. Can you tell me how is the pin configuration of any IP? It can be in a link or sample code.

 

[barry]

Most IP does not have pin constraints; that's up to you. IP is generally designed to go into more than one device which may have totally different pinouts.

What do you mean you have a "time problem"? Do you mean you don't have time to do this, or your design doesn't meet timing?

 

[stark43]

Do you mean you don't have time to do this, or your design doesn't meet timing?

I meant my workload.

I need to input the parallel camera pixels to the FPGA with "Pixel to Byte IP". My camera outputs 3.3V CMOS. I was not sure which pins I can use in Crosslink. I have the Crosslink LIF-MD6000 Master Link Board. What I'm wondering is,
1) Can we use differential CMOS inputs separately as single ended?
2) I only want to use RX Connector 1. I want to make sure that I can use pins not specified with CMOS (eg CH0_DATA1_P) as parallel CMOS pixel inputs.
Note: Instead of saying please look at the datasheet or other document, prefer to say see this section or say the answer directly if you have knowledge, because I have reviewed the documents in general.

Links
Pixel to Byte IP Doc
Crosslink Family Datasheet
CrossLink sysI/O Usage Guide

Best Regards

--- Updated Sep 28, 2022 ---

Crosslink Master Link Board Rx Connector Schematic

--- Updated Sep 28, 2022 ---

Pixel to Byte IP Block Diagram

3) Which pin can I input the pixel clock port on the FPGA?

 

[FvM]

You switched from an IP using dedicated MIPI-D PHY to IP that's entirely implemented in FPGA fabric and uses regular LVCMOS IO. Respectively there are no constraints for it except assigning appropriate VCCIO to the used IO bank(s).

I'd prefer dedicated clock pins for clock inputs as far as possible.

My general suggestion is to compile a test design to check if your pin assignment is acceptable.

 

[stark43]

Finally found an example. As far as I understand, all the pins that output CMOS33 are. As you said, it has connected the pixel clock to a pin that supports the clock input feature. I am sharing the source link, anyone who needs it can take a look. Thank you for your interest. Have a nice day.

Lattice Embedded Vision Development Kit Datasheet Section 7.1