naderi
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multiple target library in design compiler
Hello all,
In Design Compiler, when I use "set_operating_conditions" with wc and bc libs, then "report_design" shows:
Library(s) Used:
CORE90GPLVT (File: ./SYNOPSYS/PR/CORE90GPLVT/LM/CORE90GPLVT_bc_1.10V_m40C.db)
CORX90GPLVT (File: ./SYNOPSYS/PR/CORX90GPLVT/LM/CORX90GPLVT_bc_1.10V_m40C.db)
It seems DC is using the the best case lib to synthesize. Is it the normal way of synthesize in DC?
Can someone tell me what might be wrong?
Also, I have three sort of libs (bc , nom, and wc) for my technology. which one of them should be set in the "target_library" and which one in "link_library"?
Thanks,
Ali
Hello all,
In Design Compiler, when I use "set_operating_conditions" with wc and bc libs, then "report_design" shows:
Library(s) Used:
CORE90GPLVT (File: ./SYNOPSYS/PR/CORE90GPLVT/LM/CORE90GPLVT_bc_1.10V_m40C.db)
CORX90GPLVT (File: ./SYNOPSYS/PR/CORX90GPLVT/LM/CORX90GPLVT_bc_1.10V_m40C.db)
It seems DC is using the the best case lib to synthesize. Is it the normal way of synthesize in DC?
Can someone tell me what might be wrong?
Also, I have three sort of libs (bc , nom, and wc) for my technology. which one of them should be set in the "target_library" and which one in "link_library"?
Thanks,
Ali