One more question about inverter.

[EDA_hg81]

If I use RC circuit to enlarge the power rising time to the inverter and the input rising time to inverter follows the I/O rising timing set by FPAG without RC power delay.

What is the result?

Some guy said if use this way the inverter can be damaged.

Thanks.

 

[gevy]

Usually Power should act earlier than Input.
If differently that circuit may be damaged over latch-up.