Question about op amp.

[Embba]

Hi, everyone. Please, I'm trying to solve an exercise at Sedra & Smith (Microelectronic circuits) 5th edition. It is the exercise 9.33 that says: "If the input bias current of an Op Amp, used as an output adder in a 10-bit digital analog converter, must not be greater than the equivalent of 1/4 of the low significative bit, what is the maximum current that must flow in Rf for an Op Amp where the bias current is 0.5 µA?"

The answer presented is 2.046 mA, but I can't have this result.

Thank you all.

 

[tepalia02]

Have you checked the 5th edition solution here?

Microelectronic Circuits By Sedra Smith 5Th Edition Solutions - Integrated Electronics - Studocu

Share free summaries, lecture notes, exam prep and more!!

www.studocu.com

 

[BradtheRad]

I think the op amp sums 10 bits coming from a weighted resistor network. The least significant bit (LSB) conveys a tiny current compared to the MSB. The range of values is 0 to 2047 (2^11-1).

The book's answer is 4092 times 0.5 uA which is the bias spec.
4096 is a power of 2. Somewhere you're supposed to multiply 2048 by 2. But why not 4 since the exercise also mentions a spec of 1/4 of something? Is there a return path in the equation? Some 1 bits sending current into some zero bits through unknown resistances? Etc?

 

[Embba]

Have you checked the 5th edition solution here?

Microelectronic Circuits By Sedra Smith 5Th Edition Solutions - Integrated Electronics - Studocu

Share free summaries, lecture notes, exam prep and more!!

www.studocu.com

Yes, i've checked this file, but this question i've posted is on exercises section, and this file that you sent only shows the solutions for questions on problems section.

 

[Embba]

I think the op amp sums 10 bits coming from a weighted resistor network. The least significant bit (LSB) conveys a tiny current compared to the MSB. The range of values is 0 to 2047 (2^11-1).

The book's answer is 4092 times 0.5 uA which is the bias spec.
4096 is a power of 2. Somewhere you're supposed to multiply 2048 by 2. But why not 4 since the exercise also mentions a spec of 1/4 of something? Is there a return path in the equation? Some 1 bits sending current into some zero bits through unknown resistances? Etc?

I also don't know how to use this informations to solve the question.

 

[BradtheRad]

Ten bits in a DAC means that its range of voltage and current output must cover a wide ratio. The LSB is weak but a designer should enable it to overcome noise in the system. The MSB is strong and a designer should not let it overload the system. In fact when all 10 bits are high, their total voltage/current must not overload the system.

Success in a DAC has a proper balance of current levels so its resistors allow all bits to contribute their part, from MSB to LSB. Response should be linear from highest to lowest value. The MSB should not draw greater current than is available.

I'm not sure but it looks like reasonable amounts were stated for an op amp (0.5uA and 1/4). Perhaps the wording of the exercise could have been clearer. If it were me I'd want to make sure the LSB is greater than the noise floor of the op amp, yet the MSB does not cause current flow out of proportion.

 

[D.A.(Tony)Stewart]

If Ii=0.5 uA max is 1/4 LSB then when the DAC output adds 1 LSB, the Rf current will add the same and will rise 4*0.5= 2uA

Then at full scale for 10 bits or 1024 * LSB the Rf current must be 1024 * 2uA = 2.048 mA

Thus from full scale voltage Rf may be computed. Some DACS have programmable output full scale current from 2 to 20 mA. Others are 50 uA full scale with 0.1 nA nominal bias.

 

[Embba]

If Ii=0.5 uA max is 1/4 LSB then when the DAC output adds 1 LSB, the Rf current will add the same and will rise 4*0.5= 2uA

Then at full scale for 10 bits or 1024 * LSB the Rf current must be 1024 * 2uA = 2.048 mA

Thus from full scale voltage Rf may be computed. Some DACS have programmable output full scale current from 2 to 20 mA. Others are 50 uA full scale with 0.1 nA nominal bias.

Thank you for your help. I still can't understand why the Rf current will rise 4*0.5, but i'll study this point.

 

[albbg]

The summer is composed by 10 resistor of values [R, 2R, 3R...2^(N-1)R] connected between MSB, MSB-1, MSB-1...LSB] bit and inverting pin of the opamp. Let's call the feedback resitor Rf.
When only the LSB bit is connected to Vi and the others left open, the output voltage will be Vo=Vi*Rf/[(R*2^(N-1)] with 10 bits then Vo=Vi*Rf/[(R*2^9]. Using the virtual ground concept the current flowing in Rf will be Vo/Rf = Vi/[(R*2^9] and we kown this has to be equal to 4*0.5uA = 2uA then Vi=2u*R*2^9. When all the resistor will be place to Vi (all bits are active) then all the resistor will be in parallel one each other. The max current the will be Imax=Vi/Rparallel Substitutin Vi we have Imax=2u*R*2^9/Rparallel The parallel of 10 resistor scaled by factor 2 gave a valor of R/1.998 that means Imax=2u*R*2^9*1.998 = 2.046m

 

[D.A.(Tony)Stewart]

Thank you for your help. I still can't understand why the Rf current will rise 4*0.5, but i'll study this point.

The input bias current is constant at 1/4 LSB.

Therefore all DAC current change must go thru inverting Rf to inverting output.