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Op amp as comparator - can't figure this out


Newbie level 5
Oct 14, 2004
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I have a simple circuit, but it's not working as expected.
View attachment 190407

LM358 is used as simple comparator for slow input signal, it should detect when Vin goes above 2V (trimmed by POT). It works, but not as expected, ie when Vin is above Vref, Vout is only 0.8 V instead close to 5V. Tried new LM358 IC, result is same. Unless there is some hidden error in pcb, I can't figure where is the problem.
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LM158 has real weak sink current and from looking at layouts I can see that every vendor has a different compromise (and often over a series of cut-and-try, leaving unconnected devices). The load resistor is recommended because Sink is so weak.

Almost any op amp is better than LM158. Its only virtue is single supply operation on the cheap.
LM358 is the dual version of the LM324 - we use them in slower ckts and/or where the max supply rail is useful ( 32V )

if the load on the output is a grounded load then the output can go to below 5mV - which is very useful in some situations

both inputs work OK at down to -0.3 V in - on a single supply above 0v - which can be very handy too
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read part 6 !
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Op amp as comparator​

just a simple question: Why?

There are OPAMPs desingned to perform amplifier tasks.
There are COMPARATORs designed to perform comparator tasks.

They are designed differently .. each one optimized for it´s job... for a good reason.

So why not use an OPAMP as an OPAMP and a Comparator as a comparator?

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A low-cost (<U$2), rail-rail I/O general-purpose CMOS op amp with very good specs is the TLV915x, where x is 1 (single), 2(dual), or 4(quad).
It has an offset voltage of 125µV, 4.5MHz GBW, 10.5nV/√Hz noise, and 20V/µs slew-rate.
All considerations about better suited comparators are reasonable, they are however unrelated to original question "why has LM358 unexpected low output voltage".

As stated, there's no phase reversal issue in this situation. I've used LM358/LM324 for decades, I don't remember hidden characteristics. There should be a simple cause for the observed behaviour.
I think this is a process failure of unstated goals, design specs and assumptions. Even the signal source was not communicated for your source, Vin.

You have an integrating differential amplifier and expecting some output transition. The actual gain is 1+ the integral of the input Vref ,so if the signal exceeds Vin-, there was some expectation of some output (analog or digital)
yet it is always low (logic "0") because the average DC level of Vin+ was less than Vin- regardless of the peak signal.

The problem could be the input slew rate was faster than the RC feedback and when it does rise, it may push Vin higher than the common mode range of 3 to 3.5V at some point.

Keep in mind if it is saturated ( here meaning BJT forced to low output limit) there is no loop gain. The feedback cap even slows down any recovery of a low output by raising Vin-.

My opinion is that the design is the wrong choice for whatever it was intended as a comparator. If the input goes above Vin- and Vout goes high, this would further raise Vin+ pushing both inputs into the condition where phase reversal might occur which is when both inputs exceed Vcc - (1.5~2V).

Although this explains why the output might be stuck at 0.8V the Vce(sat) type of output level for this class of OpAmps, it certainly is not a comparator. It's a "1+(non-inverting) integrator" to a reference. Unfortunately, active integrators are inverting, which doesn't fit well with this unstated intention.

My recommendation is to define exactly what behaviour you want in a design spec with tolerances on inputs and outputs and try to analyze transfer functions and how gain is affected by saturation and how phase inversion is affected by exceeding Vcm on both inputs. You will find it better solutions out there after this process of design by objective rather than "trial and error". Although it did make me curious.

This will compare for you.


If you want a non-inverting integrator, just say so but add the engineering lingo with values, inputs and tolerances. We would really appreciate it and I see you are aware of input bias current induced offsets by adding R2 so that is a good thought so you want it to be pretty accurate and that is good, but how much error is tolerable goes into your design spec 1st. ( if humanly possible) ;)

Thanks (for allowing me to be a little tongue in cheek)

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