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One more question about inverter.

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EDA_hg81

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If I use RC circuit to enlarge the power rising time to the inverter and the input rising time to inverter follows the I/O rising timing set by FPAG without RC power delay.

What is the result?

Some guy said if use this way the inverter can be damaged.

Thanks.
 

gevy

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Usually Power should act earlier than Input.
If differently that circuit may be damaged over latch-up.
 

    EDA_hg81

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