give some ideas about the diffrences bettween fpga and asic :
[1] : the resource -> (especially to the fpga realization), u need to consider the resources that the fpga chip can use(eg: FFS/Memory bits/adder/multiplier/pll), so u need to be carefull of the number of the above resources your coding will occupy when after mapping to the fpga chip.
[2]: the frequency -> the most frequency value that the fpga chip supportted is fixed,as the fpga chip is composed of the basic cell ,of course the clock network(composed of the special CLK-BUF belonging to the fpga). The physical characters of the CLK-BUF and the ALU which containing FF/Latch are fixed too, so the timing requierment is relatively fixed versus to the asic) , and the verilog/vhdl mapping is based on the constrained physical characters of the fpga. So using the fpga ,you should using the pll resource fully. Of couser you should be clear about the clock/reset structure,eg, sync/async, for asic,the clock structure is very important at the synthesis step, eg, false path setting bettween async clock zones (have no datapath for function ), fast clock lauch&slow clock capture and versus,clock generation, etc. But for fpga you can change your clock structure at anytime if you want,and debug your coding with chipscope/signaltap,as fpga support erase so many times, but asic is more difficult , the clock/reset structure is vital to the following P&R step(eg,CTS), and directly affect the most frequency value, time closure,etc.
[3]:why using fpga at the asic chip design?-> in order to evaluate the structure of the system and algorithm through the asic project steps,u need to using the fpga platflorm to quickly watch the result, it's the reason why using the fpga for the asic design.
[4]:the tools of fpga VS asic design->fpga: matlap(simulink xxx.m)->ise/quartus/nios2-H/W configuaration (verilog/vhdl coding, simulation,cpu hardware/software configuration, and translate/physical mapping is realized automatically, normally u dont need so hard to change the sdc constrain like the asic design, of course u can constrain the resource mapping)->chipscope/signaltap->finished! For asic ,you just have one chance, after tape-out, everything is over! C/C plusplus/SystemC help to setup the basic structure of the top module -> Simulation(NCverilog,so many tools...)->Synthesis(DC/RC,u clock tructure now is so important,and you should write sdc file accordingly)->formality(LEC/FORMALITY, circuit equality using some model and algorithm replaced simulation which cost much more time) -> P&R(SE/ICC)->LVS/DRC(SE/ICC/CALIBER),of cource u need care about the COST/AREA/SPEED/POWER/TIME2MARKET respects(which is most important o u?u should be clear at the chip planning period), during these processes,there are so many tools,tools is not the most important,you can study the Synopsys/Cadence/Mentor/Magama's tools and other tools from diffrent companys. Rootly , tool is mostly the same bettwen different companys ,just need to control one is enough.
[5] for asic design, u need to consider the lower power technic more hardly versus for fpga. Low power is the trend for the current soc chip design.
[6] fpga give you many chances to change your fault, but asic design you have no chance otherwise u don't konw where to spend your money.